main.c

將Verilog設計轉成VHDL設計的程式

#include <stdio.h>
#include <unistd.h>
#include "main.h"

/*
extern yyparse();
extern FILE* yyin;

FILE *debug;
FILE *output;
FILE *input;

void execute(char *f_input,char *f_output,char *f_debug)
{
  unlink(f_debug);
  debug=fopen(f_debug,"w");
  yyin=fopen(f_input,"r");
  output=fopen(f_output,"w");
  yyparse();
  fclose(debug);
  fclose(yyin);
  fclose(output);
}
*/

int main(int argc,char *args[])
{
  unlink("debug.vl2vhdl");
  if(argc<3){
    fprintf(stderr,"Syntax: lexp input output [debug]\n");
    return -1;
  }
  if(argc==4)
    execute(args[1],args[2],args[3]);
  else
    execute(args[1],args[2],"debug.vl2vhdl");
  return 0;
}