filea.t_v2v

將Verilog設計轉成VHDL設計的程式

process begin
   sum <= 0;
   zero <= sum;
   sum <= in1 + in2;
   sum <=  verilog_left_shift(in1 , 2);
   i <= 0;
   while i < 10 loop
      in1 <= i;
      i <= i + 1;
   end loop;
   case ir(15 downto 12) is
      when B"010" =>
         pc <= m(ir(12 downto 0));
      when 12 | 11 =>
         acc <= acc - m(ir(2 downto 0));
      when others =>
         while ir(1 downto 0) < 2 loop
            pc <= pc + 1;
         end loop;
   end case;
   if (acc < 0) then
      pc <= pc + 1;
   else
      loop
         pc <= pc + 2;
      end loop;
   endif;
   block (
      (in2'event and in2 = '1') or in1'event
   )
   begin
      process begin
      if GUARD then
         out <= out + 1;
      end if;
      wait on GUARD;
      end process;
   end block;
end process;