lex.yy.c

將Verilog設計轉成VHDL設計的程式

YY_RULE_SETUP
#line 48 "verilog-lex"
{ return VL_RSHIFT;      }
	YY_BREAK
case 18:
YY_RULE_SETUP
#line 49 "verilog-lex"
{ return VL_CONDITIONAL; }
	YY_BREAK
case 19:
YY_RULE_SETUP
#line 51 "verilog-lex"
{ return VL_STRING; }
	YY_BREAK
case 20:
YY_RULE_SETUP
#line 53 "verilog-lex"
{ return VL_ALWAYS; }
	YY_BREAK
case 21:
YY_RULE_SETUP
#line 54 "verilog-lex"
{ return VL_ALLPATH; }
	YY_BREAK
case 22:
YY_RULE_SETUP
#line 55 "verilog-lex"
{ return VL_AND; }
	YY_BREAK
case 23:
YY_RULE_SETUP
#line 56 "verilog-lex"
{ return VL_ASSIGN; }
	YY_BREAK
case 24:
YY_RULE_SETUP
#line 57 "verilog-lex"
{ return VL_BEGIN; }
	YY_BREAK
case 25:
YY_RULE_SETUP
#line 58 "verilog-lex"
{ return VL_BUF; }
	YY_BREAK
case 26:
YY_RULE_SETUP
#line 59 "verilog-lex"
{ return VL_BUFIF0; }
	YY_BREAK
case 27:
YY_RULE_SETUP
#line 60 "verilog-lex"
{ return VL_BUFIF1; }
	YY_BREAK
case 28:
YY_RULE_SETUP
#line 61 "verilog-lex"
{ return VL_CASE; }
	YY_BREAK
case 29:
YY_RULE_SETUP
#line 62 "verilog-lex"
{ return VL_CASEX; }
	YY_BREAK
case 30:
YY_RULE_SETUP
#line 63 "verilog-lex"
{ return VL_CASEZ; }
	YY_BREAK
case 31:
YY_RULE_SETUP
#line 64 "verilog-lex"
{ return VL_CMOS; }
	YY_BREAK
case 32:
YY_RULE_SETUP
#line 65 "verilog-lex"
{ return VL_DEASSIGN; }
	YY_BREAK
case 33:
YY_RULE_SETUP
#line 66 "verilog-lex"
{ return VL_DEFAULT; }
	YY_BREAK
case 34:
YY_RULE_SETUP
#line 67 "verilog-lex"
{ return VL_DEFPARAM; }
	YY_BREAK
case 35:
YY_RULE_SETUP
#line 68 "verilog-lex"
{ return VL_DISABLE; }
	YY_BREAK
case 36:
YY_RULE_SETUP
#line 69 "verilog-lex"
{ return VL_EDGE; }
	YY_BREAK
case 37:
YY_RULE_SETUP
#line 70 "verilog-lex"
{ return VL_ELSE; }
	YY_BREAK
case 38:
YY_RULE_SETUP
#line 71 "verilog-lex"
{ return VL_END; }
	YY_BREAK
case 39:
YY_RULE_SETUP
#line 72 "verilog-lex"
{ return VL_ENDCASE; }
	YY_BREAK
case 40:
YY_RULE_SETUP
#line 73 "verilog-lex"
{ return VL_ENDFUNCTION; }
	YY_BREAK
case 41:
YY_RULE_SETUP
#line 74 "verilog-lex"
{ return VL_ENDMODULE; }
	YY_BREAK
case 42:
YY_RULE_SETUP
#line 75 "verilog-lex"
{ return VL_ENDPRIMITIVE; }
	YY_BREAK
case 43:
YY_RULE_SETUP
#line 76 "verilog-lex"
{ return VL_ENDSPECIFY; }
	YY_BREAK
case 44:
YY_RULE_SETUP
#line 77 "verilog-lex"
{ return VL_ENDTASK; }
	YY_BREAK
case 45:
YY_RULE_SETUP
#line 78 "verilog-lex"
{ return VL_EVENT; }
	YY_BREAK
case 46:
YY_RULE_SETUP
#line 79 "verilog-lex"
{ return VL_FOR; }
	YY_BREAK
case 47:
YY_RULE_SETUP
#line 80 "verilog-lex"
{ return VL_FOREVER; }
	YY_BREAK
case 48:
YY_RULE_SETUP
#line 81 "verilog-lex"
{ return VL_FORK; }
	YY_BREAK
case 49:
YY_RULE_SETUP
#line 82 "verilog-lex"
{ return VL_FUNCTION; }
	YY_BREAK
case 50:
YY_RULE_SETUP
#line 83 "verilog-lex"
{ return VL_HIGHZ0; }
	YY_BREAK
case 51:
YY_RULE_SETUP
#line 84 "verilog-lex"
{ return VL_HIGHZ1; }
	YY_BREAK
case 52:
YY_RULE_SETUP
#line 85 "verilog-lex"
{ return VL_IF; }
	YY_BREAK
case 53:
YY_RULE_SETUP
#line 86 "verilog-lex"
{ return VL_INITIAL; }
	YY_BREAK
case 54:
YY_RULE_SETUP
#line 87 "verilog-lex"
{ return VL_INOUT; }
	YY_BREAK
case 55:
YY_RULE_SETUP
#line 88 "verilog-lex"
{ return VL_INPUT; }
	YY_BREAK
case 56:
YY_RULE_SETUP
#line 89 "verilog-lex"
{ return VL_INTEGER; }
	YY_BREAK
case 57:
YY_RULE_SETUP
#line 90 "verilog-lex"
{ return VL_JOIN; }
	YY_BREAK
case 58:
YY_RULE_SETUP
#line 91 "verilog-lex"
{ return VL_LARGE; }
	YY_BREAK
case 59:
YY_RULE_SETUP
#line 92 "verilog-lex"
{ return VL_LEADTO; }
	YY_BREAK
case 60:
YY_RULE_SETUP
#line 93 "verilog-lex"
{ return VL_MACROMODULE; }
	YY_BREAK
case 61:
YY_RULE_SETUP
#line 94 "verilog-lex"
{ return VL_MEDIUM; }
	YY_BREAK
case 62:
YY_RULE_SETUP
#line 95 "verilog-lex"
{ return VL_MODULE; }
	YY_BREAK
case 63:
YY_RULE_SETUP
#line 96 "verilog-lex"
{ return VL_NBASSIGN;  }
	YY_BREAK
case 64:
YY_RULE_SETUP
#line 97 "verilog-lex"
{ return VL_NAND; }
	YY_BREAK
case 65:
YY_RULE_SETUP
#line 98 "verilog-lex"
{ return VL_NEGEDGE; }
	YY_BREAK
case 66:
YY_RULE_SETUP
#line 99 "verilog-lex"
{ return VL_NMOS; }
	YY_BREAK
case 67:
YY_RULE_SETUP
#line 100 "verilog-lex"
{ return VL_NOR; }
	YY_BREAK
case 68:
YY_RULE_SETUP
#line 101 "verilog-lex"
{ return VL_NOT; }
	YY_BREAK
case 69:
YY_RULE_SETUP
#line 102 "verilog-lex"
{ return VL_NOTIF0; }
	YY_BREAK
case 70:
YY_RULE_SETUP
#line 103 "verilog-lex"
{ return VL_NOTIF1; }
	YY_BREAK
case 71:
YY_RULE_SETUP
#line 104 "verilog-lex"
{ return VL_OR; }
	YY_BREAK
case 72:
YY_RULE_SETUP
#line 105 "verilog-lex"
{ return VL_OUTPUT; }
	YY_BREAK
case 73:
YY_RULE_SETUP
#line 106 "verilog-lex"
{ return VL_PARAMETER; }
	YY_BREAK
case 74:
YY_RULE_SETUP
#line 107 "verilog-lex"
{ return VL_PMOS; }
	YY_BREAK
case 75:
YY_RULE_SETUP
#line 108 "verilog-lex"
{ return VL_POSEDGE; }
	YY_BREAK
case 76:
YY_RULE_SETUP
#line 109 "verilog-lex"
{ return VL_PRIMITIVE; }
	YY_BREAK
case 77:
YY_RULE_SETUP
#line 110 "verilog-lex"
{ return VL_PULL0; }
	YY_BREAK
case 78:
YY_RULE_SETUP
#line 111 "verilog-lex"
{ return VL_PULL1; }
	YY_BREAK
case 79:
YY_RULE_SETUP
#line 112 "verilog-lex"
{ return VL_PULLDOWN; }
	YY_BREAK
case 80:
YY_RULE_SETUP
#line 113 "verilog-lex"
{ return VL_PULLUP; }
	YY_BREAK
case 81:
YY_RULE_SETUP
#line 114 "verilog-lex"
{ return VL_RCMOS; }
	YY_BREAK
case 82:
YY_RULE_SETUP
#line 115 "verilog-lex"
{ return VL_REAL; }
	YY_BREAK
case 83:
YY_RULE_SETUP
#line 116 "verilog-lex"
{ return VL_REG; }
	YY_BREAK
case 84:
YY_RULE_SETUP
#line 117 "verilog-lex"
{ return VL_REPEAT; }
	YY_BREAK
case 85:
YY_RULE_SETUP
#line 118 "verilog-lex"
{ return VL_RIGHTARROW; }
	YY_BREAK
case 86:
YY_RULE_SETUP
#line 119 "verilog-lex"
{ return VL_RNMOS; }
	YY_BREAK
case 87:
YY_RULE_SETUP
#line 120 "verilog-lex"
{ return VL_RPMOS; }
	YY_BREAK
case 88:
YY_RULE_SETUP
#line 121 "verilog-lex"
{ return VL_RTRAN; }
	YY_BREAK
case 89:
YY_RULE_SETUP
#line 122 "verilog-lex"
{ return VL_RTRANIF0; }
	YY_BREAK
case 90:
YY_RULE_SETUP
#line 123 "verilog-lex"
{ return VL_RTRANIF1; }
	YY_BREAK
case 91:
YY_RULE_SETUP
#line 124 "verilog-lex"
{ return VL_SCALARED; }
	YY_BREAK
case 92:
YY_RULE_SETUP
#line 125 "verilog-lex"
{ return VL_SMALL; }
	YY_BREAK
case 93:
YY_RULE_SETUP
#line 126 "verilog-lex"
{ return VL_SPECIFY; }
	YY_BREAK
case 94:
YY_RULE_SETUP
#line 127 "verilog-lex"
{ return VL_SPECPARAM; }
	YY_BREAK
case 95:
YY_RULE_SETUP
#line 128 "verilog-lex"
{ return VL_STRONG0; }
	YY_BREAK
case 96:
YY_RULE_SETUP
#line 129 "verilog-lex"
{ return VL_STRONG1; }
	YY_BREAK
case 97:
YY_RULE_SETUP
#line 130 "verilog-lex"
{ return VL_SUPPLY0; }
	YY_BREAK
case 98:
YY_RULE_SETUP
#line 131 "verilog-lex"
{ return VL_SUPPLY1; }
	YY_BREAK
case 99:
YY_RULE_SETUP
#line 132 "verilog-lex"
{ return VL_SWIRE; }
	YY_BREAK
case 100:
YY_RULE_SETUP
#line 133 "verilog-lex"
{ return VL_TASK; }
	YY_BREAK
case 101:
YY_RULE_SETUP
#line 134 "verilog-lex"
{ return VL_TIME; }
	YY_BREAK
case 102:
YY_RULE_SETUP
#line 135 "verilog-lex"
{ return VL_TRAN; }
	YY_BREAK
case 103:
YY_RULE_SETUP
#line 136 "verilog-lex"
{ return VL_TRANIF0; }
	YY_BREAK
case 104:
YY_RULE_SETUP
#line 137 "verilog-lex"
{ return VL_TRANIF1; }
	YY_BREAK
case 105:
YY_RULE_SETUP
#line 138 "verilog-lex"
{ return VL_TRI; }
	YY_BREAK
case 106:
YY_RULE_SETUP
#line 139 "verilog-lex"
{ return VL_TRI0; }
	YY_BREAK
case 107:
YY_RULE_SETUP
#line 140 "verilog-lex"
{ return VL_TRI1; }
	YY_BREAK
case 108:
YY_RULE_SETUP
#line 141 "verilog-lex"
{ return VL_TRIAND; }
	YY_BREAK
case 109:
YY_RULE_SETUP
#line 142 "verilog-lex"
{ return VL_TRIOR; }
	YY_BREAK
case 110:
YY_RULE_SETUP
#line 143 "verilog-lex"
{ return VL_VECTORED; }
	YY_BREAK
case 111:
YY_RULE_SETUP
#line 144 "verilog-lex"
{ return VL_WAIT; }
	YY_BREAK
case 112:
YY_RULE_SETUP
#line 145 "verilog-lex"
{ return VL_WAND; }
	YY_BREAK
case 113:
YY_RULE_SETUP
#line 146 "verilog-lex"
{ return VL_WEAK0; }
	YY_BREAK
case 114:
YY_RULE_SETUP
#line 147 "verilog-lex"
{ return VL_WEAK1; }
	YY_BREAK
case 115:
YY_RULE_SETUP
#line 148 "verilog-lex"
{ return VL_WHILE; }