verilog-y.tab.c

將Verilog設計轉成VHDL設計的程式

    {
      int yyi;

      YYFPRINTF (stderr, "Reducing via rule %d (line %d), ",
		 yyn, yyrline[yyn]);

      /* Print the symbols being reduced, and their result.  */
      for (yyi = yyprhs[yyn]; yyrhs[yyi] > 0; yyi++)
	YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
      YYFPRINTF (stderr, " -> %s\n", yytname[yyr1[yyn]]);
    }
#endif

  switch (yyn) {

case 2:
#line 254 "verilog-y"
{
	;
    break;}
case 3:
#line 260 "verilog-y"
{
		yyval.module=new Module(yyvsp[-4].char_ptr);
		while(!yyvsp[-1].list->empty()){
			MItemP tmp=(MItemP)yyvsp[-1].list->remove();
			/*
			if(tmp->tip==IO)
				$$->addIO(tmp->value);
			if(tmp->tip==PAR)
				$$->addPar(tmp->value);
			if(tmp->tip==INIT)
				$$->addProc(tmp->value);
			*/
			switch(tmp->tip)
			{
				case IO:
					yyval.module->addIO(tmp->value);
					break;
				case PAR:
					//$$->addPar(tmp->value);
					//break;
					{
					List *ltmp=(List*)tmp->value;
					while(!ltmp->empty()){
						PDeclP ptmp=(PDeclP)ltmp->remove();
						yyval.module->addPar(ptmp);
					}
					}
				case ALW:
				case INIT:
				case ASSIGN:	
					yyval.module->addProc(tmp->value);
					break;
				case TASK:
					yyval.module->addTask(tmp->value);
					break;	
				case NET:
				case REG:
					//BitVecP t=(BitVecP)tmp->value;
					//t->toVHDL(stdout);
					yyval.module->addNet(tmp->value);
					break;
				case MODULE:
					yyval.module->addModule(tmp->value);
					break;
			}
		}
		yyval.module->shift_l = shift_l;
		yyval.module->shift_r = shift_r;
		yyval.module->unary_or = unary_or;
		yyval.module->unary_and = unary_and;
		yyval.module->unary_nor = unary_nor;
		yyval.module->unary_nand = unary_nand;
		yyval.module->unary_xor = unary_xor;
		yyval.module->unary_nxor = unary_nxor;
		yyval.module->toVHDL(output);		
	;
    break;}
case 4:
#line 320 "verilog-y"
{
		fprintf(debug,"list_of_ports_opt: /* empty */\n");
		yyval.list=new List();
	;
    break;}
case 5:
#line 326 "verilog-y"
{
		fprintf(debug,"list_of_ports_opt: '(' ports ')'\n");
		yyval.list=yyvsp[-1].list;
	;
    break;}
case 6:
#line 334 "verilog-y"
{
		fprintf(debug,"ports: port\n");
		yyval.list=new List();
		yyval.list->add(yyvsp[0].port_decl);
		
	;
    break;}
case 7:
#line 341 "verilog-y"
{
		fprintf(debug,"ports: ports ',' port\n");
		yyvsp[-2].list->add(yyvsp[0].port_decl);
		yyval.list=yyvsp[-2].list;
	;
    break;}
case 8:
#line 350 "verilog-y"
{
		yyval.port_decl=(PortDeclP)calloc(1,sizeof(PortDecl));
		yyval.port_decl->signal=NULL;
		yyval.port_decl->var=NULL;
	;
    break;}
case 9:
#line 357 "verilog-y"
{
		yyval.port_decl=(PortDeclP)calloc(1,sizeof(PortDecl));
		fprintf(debug,"port: port_expression_opt\n");
		yyval.port_decl->var=yyvsp[0].char_ptr;
		yyval.port_decl->signal=NULL;
	;
    break;}
case 10:
#line 364 "verilog-y"
{
		yyval.port_decl=(PortDeclP)calloc(1,sizeof(PortDecl));
		fprintf(debug,"port: .VL_ID ports not implemented\n");
		yyval.port_decl->var=yyvsp[-1].char_ptr;
		yyval.port_decl->signal=yyvsp[-3].char_ptr;
	;
    break;}
case 11:
#line 376 "verilog-y"
{

	;
    break;}
case 12:
#line 382 "verilog-y"
{
		yyval.list=new List();
	;
    break;}
case 13:
#line 386 "verilog-y"
{
		//if($1==NULL)$1=new List;
		/*if($2->tip==REG)
		{
			BitVecP tmp=(BitVecP)$2->value;
			tmp->toVHDL(stdout);
		}*/
		yyvsp[-1].list->add((void*)yyvsp[0].m_item);
		yyval.list=yyvsp[-1].list;
	;
    break;}
case 14:
#line 400 "verilog-y"
{
		fprintf(debug,"module_item: parameter_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=PAR;
		yyval.m_item->value=(void*)yyvsp[0].list;
          ;
    break;}
case 15:
#line 407 "verilog-y"
{
		fprintf(debug,"module_item: input_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=IO;
		yyval.m_item->value=(void*)yyvsp[0].io_decl;
          ;
    break;}
case 16:
#line 414 "verilog-y"
{
		fprintf(debug,"module_item: output_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=IO;
		yyval.m_item->value=(void*)yyvsp[0].io_decl;
          ;
    break;}
case 17:
#line 421 "verilog-y"
{
		fprintf(debug,"module_item: inout_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=IO;
		yyval.m_item->value=(void*)yyvsp[0].io_decl;
          ;
    break;}
case 18:
#line 428 "verilog-y"
{
		fprintf(debug,"module_item: net_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=NET;
		yyval.m_item->value=(void*)yyvsp[0].bit_vec;
          ;
    break;}
case 19:
#line 435 "verilog-y"
{
		fprintf(debug,"module_item: reg_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=REG;
		yyval.m_item->value=(void*)yyvsp[0].bit_vec;
		/*$1->toVHDL(stdout);*/
          ;
    break;}
case 20:
#line 443 "verilog-y"
{
		fprintf(debug,"module_declaration: \n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=MODULE;
		yyval.m_item->value=yyvsp[0].m_decl;
	  ;
    break;}
case 21:
#line 450 "verilog-y"
{
		fprintf(debug,"module_item: initial_statement\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=INIT;
		yyval.m_item->value=yyvsp[0].pb_decl;
          ;
    break;}
case 22:
#line 457 "verilog-y"
{
		fprintf(debug,"module_item: always_statement\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=ALW;
		yyval.m_item->value=(void*)yyvsp[0].pb_decl;
          ;
    break;}
case 23:
#line 464 "verilog-y"
{
		fprintf(debug,"module_item: always_statement\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip=ALW;
		yyval.m_item->value=(void*)yyvsp[0].pb_decl;
	  ;
    break;}
case 24:
#line 471 "verilog-y"
{
		fprintf(debug,"module_item: task_declaration\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip = TASK;
		yyval.m_item->value = yyvsp[0].pb_decl;
	  ;
    break;}
case 25:
#line 478 "verilog-y"
{
		fprintf(debug,"module_item: assign\n");
		yyval.m_item=(MItemP)calloc(1,sizeof(MItem));
		yyval.m_item->tip = ASSIGN;
		yyval.m_item->value = yyvsp[0].pb_decl;
	  ;
    break;}
case 26:
#line 488 "verilog-y"
{
		fprintf(debug, "VL_ASSIGN\n");
		yyval.pb_decl=(PBDeclP)calloc(1,sizeof(PBDecl));
		yyval.pb_decl->file_name=beginproc();
		fprintf(fp,"process begin\nloop\n"); 
		buggy=yyval.pb_decl;
		t->inc();
	;
    break;}
case 27:
#line 497 "verilog-y"
{
		yyval.pb_decl=(PBDeclP)buggy;
		fprintf(debug,"assign_declaration: statement\n");
		t->dec();
		fprintf(fp,"end loop;\nend process;\n"); 
		endproc();
	;
    break;}
case 28:
#line 508 "verilog-y"
{
		fprintf(debug, "VL_TASK\n");
		yyval.pb_decl=(PBDeclP)calloc(1,sizeof(PBDecl));
		yyval.pb_decl->file_name=beginproc();
		fprintf(fp,"procedure %s(",yyvsp[-1].char_ptr); 
		buggy=yyval.pb_decl;
		t->inc();
	;
    break;}
case 29:
#line 517 "verilog-y"
{
		fprintf(fp,"\b\b);\nbegin\n");
	;
    break;}
case 30:
#line 521 "verilog-y"
{
		yyval.pb_decl=(PBDeclP)buggy;
		fprintf(fp,"end %s;\n",yyvsp[-6].char_ptr); 
		endproc();
	;
    break;}
case 31:
#line 530 "verilog-y"
{
		fprintf(debug,"io_declaration_opt_list : io_declaration_opt\n");
	;
    break;}
case 32:
#line 534 "verilog-y"
{
		fprintf(debug,"io_declaration_opt_list : io_declaration_opt_list io_declaration_opt\n");
	;
    break;}
case 33:
#line 541 "verilog-y"
{
		yyvsp[0].io_decl->toVHDL(fp);
		fprintf(fp,"; ");
		fprintf(debug,"io_declaration_opt : input_declaration\n");
	;
    break;}
case 34:
#line 547 "verilog-y"
{
		yyvsp[0].io_decl->toVHDL(fp);
		fprintf(fp,"; ");
		fprintf(debug,"io_declaration_opt : output_declaration\n");
	;
    break;}
case 35:
#line 553 "verilog-y"
{
		yyvsp[0].io_decl->toVHDL(fp);
		fprintf(fp,"; ");
		fprintf(debug,"io_declaration_opt : inout_declaration\n");
	;
    break;}
case 36:
#line 562 "verilog-y"
{
		yyval.m_decl=(MDeclP)calloc(1,sizeof(MDecl));
		fprintf(debug,"module_declaration\n");
		///printf("%s\n",$1);
		///char *ptr=$1;
		///$$