schema.fig

將Verilog設計轉成VHDL設計的程式

#FIG 3.2
Landscape
Center
Inches
Letter  
80.00
Single
-2
1200 2
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 6300 11325 6300 8775 7500 8775 7500 11325 6300 11325
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 6300 9975 4950 9975
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 4950 9075 4050 9075 4050 10875 4950 10875 4950 9075
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 4050 9975 3000 8325
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 3375 6150 2550 6150 2550 8325 3375 8325 3375 6150
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 2971 6133 4021 4408
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 4950 3300 4050 3300 4050 5550 4950 5550 4950 3300
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 6300 5700 6300 3150 7500 3150 7500 5700 6300 5700
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 4950 4425 6300 4425
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 5
	1 1 2.00 75.00 150.00
	 4500 9075 4500 7650 5400 7650 5400 1125 6450 1125
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 3375 6375 5400 6375
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 3
	1 1 2.00 75.00 150.00
	 4500 3300 4500 2475 5400 2475
2 1 0 2 0 7 100 0 -1 6.000 0 0 -1 0 0 6
	 3900 12075 3900 12225 1200 12225 1200 2100 3900 2100 3900 2250
2 2 0 3 0 7 100 0 -1 8.000 0 0 7 0 0 5
	 2400 12075 2400 2250 5925 2250 5925 12075 2400 12075
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 6450 1950 6450 225 7125 225 7125 1950 6450 1950
4 0 0 100 0 2 14 1.5708 4 150 870 4350 10650 Analizor \001
4 0 0 100 0 2 14 1.5708 4 150 630 4575 10425 lexical\001
4 0 0 100 0 2 14 1.5708 4 150 345 4800 10050 Lex\001
4 0 0 100 0 2 14 1.5708 4 150 810 2775 7950 Analizor\001
4 0 0 100 0 2 14 1.5708 4 150 795 3000 7800 sintactic\001
4 0 0 100 0 2 14 1.5708 4 195 1200 3225 7650 Bison (Yacc)\001
4 0 0 100 0 2 14 1.5708 4 150 720 3600 7725 Analiza\001
4 0 0 100 0 2 14 1.5708 4 150 900 3825 7725 sintactica\001
4 0 0 100 0 2 14 1.5708 4 195 1020 3675 10500 (terminali)\001
4 0 0 100 0 2 14 1.5708 4 150 690 3450 10200 lexicali\001
4 0 0 100 0 2 14 1.5708 4 150 660 3225 9900 Tokeni\001
4 0 0 100 0 2 14 1.5708 4 150 660 3150 5700 Arbore\001
4 0 0 100 0 2 14 1.5708 4 150 795 3375 5475 sintactic\001
4 0 0 100 0 2 14 1.5708 4 195 1080 3600 5025 (gramatica)\001
4 0 0 100 0 2 14 1.5708 4 195 2055 4350 5400 Structuri ce mapeaza \001
4 0 0 100 0 2 14 1.5708 4 195 1710 4575 5325 parti ale arborelui\001
4 0 0 100 0 2 14 1.5708 4 150 1440 4800 5175 clasa "Module"\001
4 0 0 100 0 2 14 1.5708 4 150 525 6825 5025 Sursa\001
4 0 0 100 0 2 14 1.5708 4 150 630 7125 4575 VDHL\001
4 0 0 100 0 2 14 1.5708 4 195 690 7125 10125 Verilog\001
4 0 0 100 0 2 14 1.5708 4 150 525 6825 10575 Sursa\001
4 0 0 100 0 2 14 1.5708 4 195 1215 6975 1650 pentru debug\001
4 0 0 100 0 2 14 1.5708 4 150 960 6750 1575 Informatii\001
4 0 0 100 0 2 14 1.5708 4 150 735 4650 11700 lexicala\001
4 0 0 100 0 2 14 1.5708 4 150 720 4425 11700 Analiza\001
4 0 0 100 0 2 14 1.5708 4 150 840 1800 8175 Interfata\001
4 0 0 100 0 2 14 1.5708 4 195 645 1800 7125 grafica\001
4 0 0 100 0 2 14 1.5708 4 195 1305 2100 7950 (XFree86, Qt)\001