schema.fig.bak

將Verilog設計轉成VHDL設計的程式

#FIG 3.2
Landscape
Center
Inches
Letter  
80.00
Single
-2
1200 2
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 1200 6150 3750 6150 3750 7350 1200 7350 1200 6150
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 2550 6150 2550 4800
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 3450 4800 3450 3900 1650 3900 1650 4800 3450 4800
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 2550 3900 4200 2850
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 6375 3225 6375 2400 4200 2400 4200 3225 6375 3225
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 6392 2821 8117 3871
2 4 0 2 0 7 100 0 -1 0.000 0 0 7 0 0 5
	 9225 4800 9225 3900 6975 3900 6975 4800 9225 4800
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 6825 6150 9375 6150 9375 7350 6825 7350 6825 6150
2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 8100 4800 8100 6150
2 2 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 5
	 10575 6300 12300 6300 12300 6975 10575 6975 10575 6300
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 5
	1 1 2.00 75.00 150.00
	 3450 4350 4875 4350 4875 5250 11400 5250 11400 6300
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 2
	1 1 2.00 75.00 150.00
	 6150 3225 6150 5250
2 1 1 2 0 7 100 0 -1 6.000 0 0 -1 1 0 3
	1 1 2.00 75.00 150.00
	 9225 4350 10050 4350 10050 5250
2 2 0 3 0 7 100 0 -1 8.000 0 0 7 0 0 5
	 450 2250 10275 2250 10275 5775 450 5775 450 2250
2 1 0 2 0 7 100 0 -1 6.000 0 0 -1 0 0 6
	 450 3750 300 3750 300 1050 10425 1050 10425 3750 10275 3750
4 0 0 100 0 2 14 0.0000 4 150 870 1875 4200 Analizor \001
4 0 0 100 0 2 14 0.0000 4 150 630 2100 4425 lexical\001
4 0 0 100 0 2 14 0.0000 4 150 345 2475 4650 Lex\001
4 0 0 100 0 2 14 0.0000 4 150 810 4575 2625 Analizor\001
4 0 0 100 0 2 14 0.0000 4 150 795 4725 2850 sintactic\001
4 0 0 100 0 2 14 0.0000 4 195 1200 4875 3075 Bison (Yacc)\001
4 0 0 100 0 2 14 0.0000 4 150 720 4800 3450 Analiza\001
4 0 0 100 0 2 14 0.0000 4 150 900 4800 3675 sintactica\001
4 0 0 100 0 2 14 0.0000 4 195 1020 2025 3525 (terminali)\001
4 0 0 100 0 2 14 0.0000 4 150 690 2325 3300 lexicali\001
4 0 0 100 0 2 14 0.0000 4 150 660 2625 3075 Tokeni\001
4 0 0 100 0 2 14 0.0000 4 150 660 6825 3000 Arbore\001
4 0 0 100 0 2 14 0.0000 4 150 795 7050 3225 sintactic\001
4 0 0 100 0 2 14 0.0000 4 195 1080 7500 3450 (gramatica)\001
4 0 0 100 0 2 14 0.0000 4 195 2055 7125 4200 Structuri ce mapeaza \001
4 0 0 100 0 2 14 0.0000 4 195 1710 7200 4425 parti ale arborelui\001
4 0 0 100 0 2 14 0.0000 4 150 1440 7350 4650 clasa "Module"\001
4 0 0 100 0 2 14 0.0000 4 150 525 7500 6675 Sursa\001
4 0 0 100 0 2 14 0.0000 4 150 630 7950 6975 VDHL\001
4 0 0 100 0 2 14 0.0000 4 195 690 2400 6975 Verilog\001
4 0 0 100 0 2 14 0.0000 4 150 525 1950 6675 Sursa\001
4 0 0 100 0 2 14 0.0000 4 195 1215 10875 6825 pentru debug\001
4 0 0 100 0 2 14 0.0000 4 150 960 10950 6600 Informatii\001
4 0 0 100 0 2 14 0.0000 4 150 735 825 4500 lexicala\001
4 0 0 100 0 2 14 0.0000 4 150 720 825 4275 Analiza\001
4 0 0 100 0 2 14 0.0000 4 150 840 4350 1650 Interfata\001
4 0 0 100 0 2 14 0.0000 4 195 645 5400 1650 grafica\001
4 0 0 100 0 2 14 0.0000 4 195 1305 4575 1950 (XFree86, Qt)\001