module.cpp

將Verilog設計轉成VHDL設計的程式

#include <string.h>
#include <stdio.h>
#include "Module.h"
#include "IODecl.h"
#include "Util.h"
#include "BitVec.h"


Module::Module(){
}

void Module::setName(char *name){
  /*int len=strlen(name)+1;
  _name=new char[len];
  strcpy(_name,name);*/
  _name=name;
}

void Module::addIO(void *io)
{
  _io.add(io);
}

void Module::addPar(void *par)
{
  _par.add(par);
}

void Module::addProc(void *proc)
{
  _proc.add(proc);
}

void Module::addNet(void *net)
{
  _net.add(net);
}

void Module::addModule(void *module)
{
  _module.add(module);
}

void Module::addTask(void *task)
{
  _task.add(task);
}

void Module::toVHDL(FILE *fp){
  
  //if(fp==NULL)
  //  fp=stdout;
  
  if(shift_l!=0)file2file(fp,"../vhdl_f/shift_l.exe");
  if(shift_r!=0)file2file(fp,"../vhdl_f/shift_r.exe");
  if(unary_or!=0)file2file(fp,"../vhdl_f/unary_and.exe");
  if(unary_and!=0)file2file(fp,"../vhdl_f/unary_and.exe");
  if(unary_nor!=0)file2file(fp,"../vhdl_f/unary_nor.exe");
  if(unary_nand!=0)file2file(fp,"../vhdl_f/unary_nand.exe");
  if(unary_xor!=0)file2file(fp,"../vhdl_f/unary_xor.exe");
  if(unary_nxor!=0)file2file(fp,"../vhdl_f/unary_nxor.exe");
  
  fprintf(fp,"entity %s is\n",_name);
  if(!_par.empty()){
    fprintf(fp,"generic(");
    while(!_par.empty()){
      PDeclP tmp=(PDeclP)_par.remove();
      fprintf(fp,"%s : signed_word_int := %s",tmp->name,tmp->expres);
      if(!_par.empty())
	fprintf(fp,"; ");
    }
  
  fprintf(fp,");\n");
  }
  if(!_io.empty()){
    fprintf(fp,"port(");
    while(!_io.empty()){
      IODeclP tmp=(IODeclP)_io.remove();
      tmp->toVHDL(fp);
      if(!_io.empty())
	fprintf(fp,";\n     ");
    }
    fprintf(fp,");\n");
  }
  fprintf(fp,"end %s;\n",_name);
  fprintf(fp,"\narhitecture VL2VHDL of %s is\n",_name);
  
  while(!_net.empty()){
    BitVecP tmp=(BitVecP)_net.remove();
    tmp->toVHDL(fp);
  }

  List mitmp;
  _module.reset_enum();
  while(!_module.stop_enum()){
    MDeclP tmp=(MDeclP)_module.next_enum();
    if(!mitmp.exist(tmp->mname)){
      fprintf(fp,"component %s\nport(",tmp->mname);
      mitmp.add(tmp->mname);
      List *ports_tmp=tmp->ports;
      ports_tmp->reset_enum();
      while(!ports_tmp->stop_enum()){
	PortDeclP pdtmp=(PortDeclP)ports_tmp->next_enum();
	fprintf(fp,"%s unknown_io_type",pdtmp->signal);
	if(!ports_tmp->stop_enum())
	  fprintf(fp,"; ");
      }
      fprintf(fp,");\nend component;\n");
    }
  }
  
  while(!_module.empty()){
    MDeclP tmp=(MDeclP)_module.remove();
    fprintf(fp,"%s : %s\nport_map(",tmp->iname,tmp->mname);
    List *ports_tmp=tmp->ports;
    while(!ports_tmp->empty()){
      PortDeclP pdtmp=(PortDeclP)ports_tmp->remove();
      fprintf(fp,"%s => %s",pdtmp->signal,pdtmp->var);
	if(!ports_tmp->empty())
	  fprintf(fp,", ");
    }
    fprintf(fp,");\n");
  } 
  
  while(!_task.empty()){
   PBDeclP tmp=(PBDeclP)_task.remove();
    file2file(fp,tmp->file_name);
  } 
  
  /** End arhitecture declarative part **/
  
  fprintf(fp,"begin\n");
  while(!_proc.empty()){
    PBDeclP tmp=(PBDeclP)_proc.remove();
    file2file(fp,tmp->file_name);
  }
  fprintf(fp,"end VL2VHDL;\n");
}