bitvec.cpp

將Verilog設計轉成VHDL設計的程式

#include "BitVec.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include "Util.h"

BitVec::BitVec(BVtype tip,List *list_of_variables,char *range_opt){
    _tip=tip;
    _list_of_variables=list_of_variables;
    _range_opt=(char*)calloc(strlen(range_opt)+1,sizeof(char));
    strcpy(_range_opt,range_opt);
}

void BitVec::toVHDL(FILE *fp){
  if(_tip==BV_REG){
    while(!_list_of_variables->empty()){
      RVarP tmp=(RVarP)_list_of_variables->remove();
      fprintf(fp,"signal %s : ",tmp->name);
      if(tmp->tip==MEMORY){
	fprintf(fp,"array %s of Bit_vector %s;\n",tmp->extra,_range_opt);
      }
      if(tmp->tip==REGISTER){
	if(_range_opt[0]=='\0')
	  fprintf(fp,"Bit;\n");
	else
	  fprintf(fp,"Bit_vector %s;\n",_range_opt);
      }
    }
  }
  if(_tip==BV_NET){
    while(!_list_of_variables->empty()){
      char* tmp=(char *)_list_of_variables->remove();
      fprintf(fp,"signal %s:",tmp);
      if(_range_opt[0]=='\0')
	  fprintf(fp,"Bit;\n");
	else
	  fprintf(fp,"Bit_vector %s;\n",_range_opt);
    }
  }
}