module.h

將Verilog設計轉成VHDL設計的程式

#ifndef Module_H
#define Module_H
#include "List.h"
#include "VL2VHDL.h"

class Module : public VL2VHDL
{
public:
  Module();
  Module(char *name){setName(name);}
  void setName(char *name);
  char *getName(){return _name;}
  void addIO(void *io);
  void addPar(void *par);
  void addProc(void *proc);
  void addNet(void *net);
  void addModule(void *module);
  void addTask(void *task);
  void toVHDL(FILE *fp);
private:
  char *_name;
  List _io;
  List _par;
  List _net;
  List _proc;
  List _module;
  List _task;
public:
  short shift_l,shift_r,unary_or,unary_and,unary_nor,unary_nand,unary_xor,unary_nxor;
};

typedef Module* ModuleP;

#endif