util.h

將Verilog設計轉成VHDL設計的程式

#ifndef Util_H
#define Util_H

#include "List.h"

#define max(a,b) (((a) > (b)) ? (a) : (b))
#define mim(a,b) (((a) < (b)) ? (a) : (b))


typedef enum{PAR,IO,NET,REG,INIT,ALW,MODULE,TASK,ASSIGN}IType;

typedef enum{REGISTER,MEMORY}RVType;

typedef struct{
  IType tip;
  void *value;
}MItem;
typedef MItem* MItemP;

typedef struct{
  char *name;
  char *expres;
}PDecl;               //parameter declaration
typedef PDecl* PDeclP;

typedef struct{
  char *extra;
  char *file_name;
}PBDecl;              //procedural block
typedef PBDecl* PBDeclP;

typedef struct{
  char *name;
  char *extra;
  RVType tip;
}RVar;                //register variable
typedef RVar* RVarP;

typedef struct{
  char *mname;
  char *iname;
  List *ports;
}MDecl;               //module declaration
typedef MDecl* MDeclP;

typedef struct{
  char *signal;
  char *var;
}PortDecl;
typedef PortDecl* PortDeclP;

char *expres3(const char *$1,const char *$2,const char*$3);
char *expres2(const char *$1,const char *$2);
char *edge_event(char*s);
void file2file(FILE *fp,char *file_name);

char *binary(char *s);
char *decimal(char *s);
char *octal(char *s);
char *hexa(char *s);

void dumm_test(char *s);

char *clean(char *s);

class Tab
{
 public:
  Tab(){i=0;}
  void printTab(FILE *fp);
  void inc(){i++;}
  void dec(){i--;}
  void null(){i=0;}
 private:
  short i;
};

#endif