iodecl.cpp

將Verilog設計轉成VHDL設計的程式

#include "IODecl.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>

IODecl::IODecl(type tip,List *list_of_variables,char *range_opt){
    _tip=tip;
    _list_of_variables=list_of_variables;
    _range_opt=range_opt;
}

/*
char* IODecl::toVHDL(){
  char *ptr=(char*)calloc(MAXIO,sizeof(char));
  char *tmp;
  ptr[0]='\0';
  while(!_list_of_variables->empty()){
    tmp=(char*)_list_of_variables->remove();
    strcat(ptr,tmp);
    strcat(ptr,", ");
  }
  ptr[strlen(ptr)-2]='\0';
  strcat(ptr," : ");
  if(_tip!=OUT)
    strcat(ptr,"In ");
  if(_tip!=IN)
    strcat(ptr,"Out ");
  if(_range_opt[0]!='\0'){
    strcat(ptr,"bit_vector");
    strcat(ptr,_range_opt);
  }
  else
    strcat(ptr,"bit");
  strcat(ptr,";");
  realloc((void*)ptr,strlen(ptr)+1);
}
*/

void IODecl::toVHDL(FILE *fp){
  char *ptr=(char*)calloc(MAXIO,sizeof(char));
  char *tmp;
  ptr[0]='\0';
  while(!_list_of_variables->empty()){
    tmp=(char*)_list_of_variables->remove();
    strcat(ptr,tmp);
    strcat(ptr,", ");
  }
  ptr[strlen(ptr)-2]='\0';
  strcat(ptr," : ");
  if(_tip!=OUT)
    strcat(ptr,"in ");
  if(_tip!=IN)
    strcat(ptr,"out ");
  if(_range_opt[0]!='\0'){
    strcat(ptr,"bit_vector");
    strcat(ptr,_range_opt);
  }
  else
    strcat(ptr,"bit");
  realloc((void*)ptr,strlen(ptr)+1);
  fprintf(fp,"%s",ptr);
  free(ptr);
}