tasks.v

將Verilog設計轉成VHDL設計的程式

module tasks;

reg R,p;

task add;      // task definition
 input a, b;   // two input argument ports
 output c;     // one output argument port
 begin
   R = 1;
   if (a == b)
     c = 1 & R;
   else
     c = 0;
 end
endtask

initial begin
   add(1, 0, p);
end

endmodule