light.v2

將Verilog設計轉成VHDL設計的程式

entity traffic is
generic(on : signed_word_int := 1; off : signed_word_int := 0; red_tics : signed_word_int := 35; amber_tics : signed_word_int := 3; green_tics : signed_word_int := 20);
end traffic;

arhitecture VL2VHDL of traffic is
signal green : Bit;
signal amber : Bit;
signal red : Bit;
signal clock : Bit;
procedure light(color : out bit; tics : in bit_vector(31 downto 0); );
begin
   i <= 0;
   while i < tics loop
      if (clock = 1) then
         color <= off;
      end if;
      i <= i + 1;
   end loop;
end light;
begin
process begin
   red <= off;
   amber <= off;
   green <= off;
end process;
process begin
loop
   clock <= 0;
   clock <= 1;
end loop;
end process;
process begin
loop
   red <= on;
   light (red,red_tics);
   green <= on;
   light (green,green_tics);
   amber <= on;
   light (amber,amber_tics);
end loop;
end process;
end VL2VHDL;