light.v~

將Verilog設計轉成VHDL設計的程式

// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
          amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;


// initialize the lights and set up monitoring of registers
initial begin
    red = off; amber = off; green = off;
end

// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
   output color;
   input [31:0] tics;
   begin
      repeat(tics)  // wait to detect tics positive edges on clock
         @(posedge clock);
      color = off;
   end
endtask

// waveform for clock period of 2 time units
always begin
  clock = 0;
  clock = 1;
end

always begin: main_process
   red = on;
   light(red, red_tics);
   green = on;
   light(green, green_tics);
   amber = on;
   light(amber, amber_tics);
end

endmodule