test.v

將Verilog設計轉成VHDL設計的程式

module adder4 (in1, in2, sum, zero);
parameter WORD = 32 ;
parameter MEMSIZE = 16 ;
input [WORD-1:0] in1, in2;
inout [11:3] busl;
output [15:0] out;
/*af*/
initial begin
	sum=0;
	zero=sum;
	sum=in1+in2;
	sum = in1 << 2;
	for(i=0 ; i<10 ; i=i+1)
		in1=i;
	case(ir[15:12])
		3'b010 : pc = m[ir[12:0]];
		11,
		12: acc=acc-m[ir[2:0]];
		default: while(ir[1:0]<2) pc=pc+1;
	endcase
	if(acc < 0) pc=pc+1;
	else
		forever pc=pc+2;
	@(posedge in2 or in1) begin
		out=out+1;
	end    
end

endmodule