tasks.v2

將Verilog設計轉成VHDL設計的程式

entity tasks is
end tasks;

arhitecture VL2VHDL of tasks is
signal p : Bit;
signal R : Bit;
procedure add(b, a : in bit; c : out bit; );
begin
   R <= 1;
   if (a = b) then
      c <= 1 and R;
   else
      c <= 0;
   endif;
end add;
begin
process begin
   add (1,0,p);
end process;
end VL2VHDL;