mark1.v

將Verilog設計轉成VHDL設計的程式

module mark1;
	reg [31:0] m[0:8191]; // 8192 x 32 bit memory
	reg [12:0] pc;        // 13 bit program counter
	reg [31:0] acc;       // 32 bit accumulator
	reg [15:0] ir;        // 16 bit instruction register

	always
	  begin
		ir = m[pc];   // fetch an instruction

		case( ir[15:13])
		  3'b000: pc = m[ir[12:0]];
		  3'b001: pc = pc + m[ir[12:0]];
		  3'b010: acc = -m[ir[12:0]];
		  3'b011: m[ir[12:0]] = acc;
		  3'b100,
		  3'b101: acc = acc - m[ir[12:0]];
		  3'b110: if(acc < 32'b0 ) pc = pc + 13'b1;
		endcase

		pc = pc + 13'b1;
	 end
endmodule