and.v2

来自「將Verilog設計轉成VHDL設計的程式」· V2 代码 · 共 17 行

entity AND is
port(in2, in1 : in bit;
     out : out bit);
end AND;

arhitecture VL2VHDL of AND is
signal w1:Bit;
component NAND
port((null) unknown_io_type; (null) unknown_io_type; (null) unknown_io_type);
end component;
NAND1 : NAND
port_map((null) => w1, (null) => in2, (null) => in1);
NAND2 : NAND
port_map((null) => out, (null) => w1, (null) => w1);
begin
end VL2VHDL;