adder4.v

来自「將Verilog設計轉成VHDL設計的程式」· Verilog 代码 · 共 22 行

module adder4 (in1, in2, sum, zero);
input [3:0] in1;
input [3:0] in2;
output [4:0] sum;
output zero;
reg [4:0] sum,m[0:32];

initial begin
   sum = 4'b0;
   zero = 4'b1;
end

always @(in1 or in2) begin
   sum = in1 + in2;
   if (sum == 4'b0)
      zero = 4'b1;
   else
      zero = 4'b0;
end

endmodule