mark1.v2

將Verilog設計轉成VHDL設計的程式

entity mark1 is
end mark1;

arhitecture VL2VHDL of mark1 is
signal m : array (0 to 8191) of Bit_vector (31 downto 0);
signal pc : Bit_vector (12 downto 0);
signal acc : Bit_vector (31 downto 0);
signal ir : Bit_vector (15 downto 0);
begin
process begin
loop
   ir <= m(pc);
   case ir(15 downto 13) is
      when B"000" =>
         pc <= m(ir(12 downto 0));
      when B"001" =>
         pc <= pc + m(ir(12 downto 0));
      when B"010" =>
         acc <= -m(ir(12 downto 0));
      when B"011" =>
         m(ir(12 downto 0)) <= acc;
      when B"101" | B"100" =>
         acc <= acc - m(ir(12 downto 0));
      when B"110" =>
         if (acc < B"00000000000000000000000000000000") then
            pc <= pc + B"0000000000001";
         end if;
   end case;
   pc <= pc + B"0000000000001";
end loop;
end process;
end VL2VHDL;