makefile

將Verilog設計轉成VHDL設計的程式

all:
	cd classes && $(MAKE)
	cd parser && $(MAKE)
	cd qt_client && $(MAKE)
	ln -s ./bin/qtvl ../qt_client/qtvl  
	echo "Kernel updated."

clean: 
	cd classes && $(MAKE) clean
	cd parser && $(MAKE) clean
	cd qt_client && $(MAKE) clean
	echo "Nuclear plant panic: core dumped."