entity.cpp

扰码程序

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "simprim.auxlib/vpackage/vpackage.h"
#include "simprim.auxlib/vcomponents/vcomponents.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/scrambler/entity.h"

static const char *entFileName = "C:/scrambler/scrambler_timesim.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_scrambler::Work_scrambler(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"scrambler", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 8)

{
  SE[0].initialize("load", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn, HSimSA::charToMem(1));
  ;
  ;
  SE[1].initialize("clock", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn, HSimSA::charToMem(1));
  ;
  ;
  SE[2].initialize("datain", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn, HSimSA::charToMem(1));
  ;
  ;
  SE[3].initialize("dataout", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigOut);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SetPorts();
 
}

Work_scrambler::~Work_scrambler()
{
}

void Work_scrambler::SetPorts()
{
}

void Work_scrambler::constructEntityObject()
{
;
}