generator_and2.vhd

sin產生器

library IEEE;
use IEEE.std_logic_1164.all;

entity generator_and2 is
port (
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC
);
end entity;



architecture and_anGen_arch of generator_and2 is
begin
O <= I0 and I1;
end architecture and_anGen_arch;