test.hier_info

sin產生器

|test
Q[0] <= generator:inst.Q[0]
Q[1] <= generator:inst.Q[1]
Q[2] <= generator:inst.Q[2]
Q[3] <= generator:inst.Q[3]
Q[4] <= generator:inst.Q[4]
Q[5] <= generator:inst.Q[5]
Q[6] <= generator:inst.Q[6]
Q[7] <= generator:inst.Q[7]
Q[8] <= generator:inst.Q[8]
Q[9] <= generator:inst.Q[9]
Q[10] <= generator:inst.Q[10]
Q[11] <= generator:inst.Q[11]
PR => generator:inst.PR
FR => generator:inst.FR
CLR => generator:inst.CLR
CE => generator:inst.CE
CLK => generator:inst.CLK
DATA[0] => generator:inst.DATA[0]
DATA[1] => generator:inst.DATA[1]
DATA[2] => generator:inst.DATA[2]
DATA[3] => generator:inst.DATA[3]
DATA[4] => generator:inst.DATA[4]
DATA[5] => generator:inst.DATA[5]
DATA[6] => generator:inst.DATA[6]
DATA[7] => generator:inst.DATA[7]
DATA[8] => generator:inst.DATA[8]
DATA[9] => generator:inst.DATA[9]


|test|generator:inst
DATA[0] => generator_reg6:U2.DATA[0]
DATA[0] => generator_reg6:U1.DATA[0]
DATA[1] => generator_reg6:U2.DATA[1]
DATA[1] => generator_reg6:U1.DATA[1]
DATA[2] => generator_reg6:U2.DATA[2]
DATA[2] => generator_reg6:U1.DATA[2]
DATA[3] => generator_reg6:U2.DATA[3]
DATA[3] => generator_reg6:U1.DATA[3]
DATA[4] => generator_reg6:U2.DATA[4]
DATA[4] => generator_reg6:U1.DATA[4]
DATA[5] => generator_reg6:U2.DATA[5]
DATA[5] => generator_reg6:U1.DATA[5]
DATA[6] => generator_reg6:U2.DATA[6]
DATA[6] => generator_reg6:U1.DATA[6]
DATA[7] => generator_reg6:U2.DATA[7]
DATA[7] => generator_reg6:U1.DATA[7]
DATA[8] => generator_reg6:U2.DATA[8]
DATA[8] => generator_reg6:U1.DATA[8]
DATA[9] => generator_reg6:U2.DATA[9]
DATA[9] => generator_reg6:U1.DATA[9]
PR => generator_and2:U9.I1
FR => generator_and2:U8.I1
CLR => generator_reg8:U7.CLR
CLR => generator_acc6:U4.CLR
CLR => generator_reg6:U2.CLR
CLR => generator_reg6:U1.CLR
CE => generator_and2:U9.I0
CE => generator_and2:U8.I0
CE => generator_reg8:U7.CE
CE => generator_acc6:U4.CE
Q[0] <= generator_reg8:U7.Q[0]
Q[1] <= generator_reg8:U7.Q[1]
Q[2] <= generator_reg8:U7.Q[2]
Q[3] <= generator_reg8:U7.Q[3]
Q[4] <= generator_reg8:U7.Q[4]
Q[5] <= generator_reg8:U7.Q[5]
Q[6] <= generator_reg8:U7.Q[6]
Q[7] <= generator_reg8:U7.Q[7]
Q[8] <= generator_reg8:U7.Q[8]
Q[9] <= generator_reg8:U7.Q[9]
Q[10] <= generator_reg8:U7.Q[10]
Q[11] <= generator_reg8:U7.Q[11]
CLK => generator_reg8:U7.CLK
CLK => generator_acc6:U4.CLK
CLK => generator_reg6:U2.CLK
CLK => generator_reg6:U1.CLK


|test|generator:inst|generator_reg6:U1
CLR => TEMP_Q_0[9].ACLR
CLR => TEMP_Q_0[8].ACLR
CLR => TEMP_Q_0[7].ACLR
CLR => TEMP_Q_0[6].ACLR
CLR => TEMP_Q_0[5].ACLR
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[0].ACLR
CE => TEMP_Q_0[9].ENA
CE => TEMP_Q_0[8].ENA
CE => TEMP_Q_0[7].ENA
CE => TEMP_Q_0[6].ENA
CE => TEMP_Q_0[5].ENA
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[0].ENA
CLK => TEMP_Q_0[9].CLK
CLK => TEMP_Q_0[8].CLK
CLK => TEMP_Q_0[7].CLK
CLK => TEMP_Q_0[6].CLK
CLK => TEMP_Q_0[5].CLK
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[0].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
DATA[6] => TEMP_Q_0[6].DATAIN
DATA[7] => TEMP_Q_0[7].DATAIN
DATA[8] => TEMP_Q_0[8].DATAIN
DATA[9] => TEMP_Q_0[9].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP_Q_0[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP_Q_0[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= TEMP_Q_0[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= TEMP_Q_0[9].DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_sin:U6
OE => Q[11]~11.OE
OE => Q[10]~10.OE
OE => Q[9]~9.OE
OE => Q[8]~8.OE
OE => Q[7]~7.OE
OE => Q[6]~6.OE
OE => Q[5]~5.OE
OE => Q[4]~4.OE
OE => Q[3]~3.OE
OE => Q[2]~2.OE
OE => Q[1]~1.OE
OE => Q[0]~0.OE
ADDRESS[0] => Mux11.IN1033
ADDRESS[0] => Mux10.IN1033
ADDRESS[0] => Mux9.IN1033
ADDRESS[0] => Mux8.IN1033
ADDRESS[0] => Mux7.IN1033
ADDRESS[0] => Mux6.IN1033
ADDRESS[0] => Mux5.IN1033
ADDRESS[0] => Mux4.IN1033
ADDRESS[0] => Mux3.IN1033
ADDRESS[0] => Mux2.IN1033
ADDRESS[0] => Mux1.IN1033
ADDRESS[0] => Mux0.IN1033
ADDRESS[1] => Mux11.IN1032
ADDRESS[1] => Mux10.IN1032
ADDRESS[1] => Mux9.IN1032
ADDRESS[1] => Mux8.IN1032
ADDRESS[1] => Mux7.IN1032
ADDRESS[1] => Mux6.IN1032
ADDRESS[1] => Mux5.IN1032
ADDRESS[1] => Mux4.IN1032
ADDRESS[1] => Mux3.IN1032
ADDRESS[1] => Mux2.IN1032
ADDRESS[1] => Mux1.IN1032
ADDRESS[1] => Mux0.IN1032
ADDRESS[2] => Mux11.IN1031
ADDRESS[2] => Mux10.IN1031
ADDRESS[2] => Mux9.IN1031
ADDRESS[2] => Mux8.IN1031
ADDRESS[2] => Mux7.IN1031
ADDRESS[2] => Mux6.IN1031
ADDRESS[2] => Mux5.IN1031
ADDRESS[2] => Mux4.IN1031
ADDRESS[2] => Mux3.IN1031
ADDRESS[2] => Mux2.IN1031
ADDRESS[2] => Mux1.IN1031
ADDRESS[2] => Mux0.IN1031
ADDRESS[3] => Mux11.IN1030
ADDRESS[3] => Mux10.IN1030
ADDRESS[3] => Mux9.IN1030
ADDRESS[3] => Mux8.IN1030
ADDRESS[3] => Mux7.IN1030
ADDRESS[3] => Mux6.IN1030
ADDRESS[3] => Mux5.IN1030
ADDRESS[3] => Mux4.IN1030
ADDRESS[3] => Mux3.IN1030
ADDRESS[3] => Mux2.IN1030
ADDRESS[3] => Mux1.IN1030
ADDRESS[3] => Mux0.IN1030
ADDRESS[4] => Mux11.IN1029
ADDRESS[4] => Mux10.IN1029
ADDRESS[4] => Mux9.IN1029
ADDRESS[4] => Mux8.IN1029
ADDRESS[4] => Mux7.IN1029
ADDRESS[4] => Mux6.IN1029
ADDRESS[4] => Mux5.IN1029
ADDRESS[4] => Mux4.IN1029
ADDRESS[4] => Mux3.IN1029
ADDRESS[4] => Mux2.IN1029
ADDRESS[4] => Mux1.IN1029
ADDRESS[4] => Mux0.IN1029
ADDRESS[5] => Mux11.IN1028
ADDRESS[5] => Mux10.IN1028
ADDRESS[5] => Mux9.IN1028
ADDRESS[5] => Mux8.IN1028
ADDRESS[5] => Mux7.IN1028
ADDRESS[5] => Mux6.IN1028
ADDRESS[5] => Mux5.IN1028
ADDRESS[5] => Mux4.IN1028
ADDRESS[5] => Mux3.IN1028
ADDRESS[5] => Mux2.IN1028
ADDRESS[5] => Mux1.IN1028
ADDRESS[5] => Mux0.IN1028
ADDRESS[6] => Mux11.IN1027
ADDRESS[6] => Mux10.IN1027
ADDRESS[6] => Mux9.IN1027
ADDRESS[6] => Mux8.IN1027
ADDRESS[6] => Mux7.IN1027
ADDRESS[6] => Mux6.IN1027
ADDRESS[6] => Mux5.IN1027
ADDRESS[6] => Mux4.IN1027
ADDRESS[6] => Mux3.IN1027
ADDRESS[6] => Mux2.IN1027
ADDRESS[6] => Mux1.IN1027
ADDRESS[6] => Mux0.IN1027
ADDRESS[7] => Mux11.IN1026
ADDRESS[7] => Mux10.IN1026
ADDRESS[7] => Mux9.IN1026
ADDRESS[7] => Mux8.IN1026
ADDRESS[7] => Mux7.IN1026
ADDRESS[7] => Mux6.IN1026
ADDRESS[7] => Mux5.IN1026
ADDRESS[7] => Mux4.IN1026
ADDRESS[7] => Mux3.IN1026
ADDRESS[7] => Mux2.IN1026
ADDRESS[7] => Mux1.IN1026
ADDRESS[7] => Mux0.IN1026
ADDRESS[8] => Mux11.IN1025
ADDRESS[8] => Mux10.IN1025
ADDRESS[8] => Mux9.IN1025
ADDRESS[8] => Mux8.IN1025
ADDRESS[8] => Mux7.IN1025
ADDRESS[8] => Mux6.IN1025
ADDRESS[8] => Mux5.IN1025
ADDRESS[8] => Mux4.IN1025
ADDRESS[8] => Mux3.IN1025
ADDRESS[8] => Mux2.IN1025
ADDRESS[8] => Mux1.IN1025
ADDRESS[8] => Mux0.IN1025
ADDRESS[9] => Mux11.IN1024
ADDRESS[9] => Mux10.IN1024
ADDRESS[9] => Mux9.IN1024
ADDRESS[9] => Mux8.IN1024
ADDRESS[9] => Mux7.IN1024
ADDRESS[9] => Mux6.IN1024
ADDRESS[9] => Mux5.IN1024
ADDRESS[9] => Mux4.IN1024
ADDRESS[9] => Mux3.IN1024
ADDRESS[9] => Mux2.IN1024
ADDRESS[9] => Mux1.IN1024
ADDRESS[9] => Mux0.IN1024
Q[0] <= Q[0]~0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~1.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~2.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~3.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~4.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~5.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~6.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~7.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q[8]~8.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q[9]~9.DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q[10]~10.DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= Q[11]~11.DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_reg6:U2
CLR => TEMP_Q_0[9].ACLR
CLR => TEMP_Q_0[8].ACLR
CLR => TEMP_Q_0[7].ACLR
CLR => TEMP_Q_0[6].ACLR
CLR => TEMP_Q_0[5].ACLR
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[0].ACLR
CE => TEMP_Q_0[9].ENA
CE => TEMP_Q_0[8].ENA
CE => TEMP_Q_0[7].ENA
CE => TEMP_Q_0[6].ENA
CE => TEMP_Q_0[5].ENA
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[0].ENA
CLK => TEMP_Q_0[9].CLK
CLK => TEMP_Q_0[8].CLK
CLK => TEMP_Q_0[7].CLK
CLK => TEMP_Q_0[6].CLK
CLK => TEMP_Q_0[5].CLK
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[0].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
DATA[6] => TEMP_Q_0[6].DATAIN
DATA[7] => TEMP_Q_0[7].DATAIN
DATA[8] => TEMP_Q_0[8].DATAIN
DATA[9] => TEMP_Q_0[9].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP_Q_0[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP_Q_0[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= TEMP_Q_0[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= TEMP_Q_0[9].DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_adder:U3
A[0] => Add0.IN10
A[1] => Add0.IN9
A[2] => Add0.IN8
A[3] => Add0.IN7
A[4] => Add0.IN6
A[5] => Add0.IN5
A[6] => Add0.IN4
A[7] => Add0.IN3
A[8] => Add0.IN2
A[9] => Add0.IN1
B[0] => Add0.IN20
B[1] => Add0.IN19
B[2] => Add0.IN18
B[3] => Add0.IN17
B[4] => Add0.IN16
B[5] => Add0.IN15
B[6] => Add0.IN14
B[7] => Add0.IN13
B[8] => Add0.IN12
B[9] => Add0.IN11
Q[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_acc6:U4
CLK => REG_Q[9].CLK
CLK => REG_Q[8].CLK
CLK => REG_Q[7].CLK
CLK => REG_Q[6].CLK
CLK => REG_Q[5].CLK
CLK => REG_Q[4].CLK
CLK => REG_Q[3].CLK
CLK => REG_Q[2].CLK
CLK => REG_Q[1].CLK
CLK => REG_Q[0].CLK
CE => REG_Q[9].ENA
CE => REG_Q[8].ENA
CE => REG_Q[7].ENA
CE => REG_Q[6].ENA
CE => REG_Q[5].ENA
CE => REG_Q[4].ENA
CE => REG_Q[3].ENA
CE => REG_Q[2].ENA
CE => REG_Q[1].ENA
CE => REG_Q[0].ENA
CLR => REG_Q[9].ACLR
CLR => REG_Q[8].ACLR
CLR => REG_Q[7].ACLR
CLR => REG_Q[6].ACLR
CLR => REG_Q[5].ACLR
CLR => REG_Q[4].ACLR
CLR => REG_Q[3].ACLR
CLR => REG_Q[2].ACLR
CLR => REG_Q[1].ACLR
CLR => REG_Q[0].ACLR
A[0] => Add0.IN10
A[1] => Add0.IN9
A[2] => Add0.IN8
A[3] => Add0.IN7
A[4] => Add0.IN6
A[5] => Add0.IN5
A[6] => Add0.IN4
A[7] => Add0.IN3
A[8] => Add0.IN2
A[9] => Add0.IN1
Q[0] <= REG_Q[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REG_Q[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REG_Q[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REG_Q[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REG_Q[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REG_Q[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= REG_Q[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= REG_Q[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= REG_Q[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= REG_Q[9].DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_reg8:U7
CLR => TEMP_Q_1[11].ACLR
CLR => TEMP_Q_1[10].ACLR
CLR => TEMP_Q_1[9].ACLR
CLR => TEMP_Q_1[8].ACLR
CLR => TEMP_Q_1[7].ACLR
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[0].ACLR
CE => TEMP_Q_1[11].ENA
CE => TEMP_Q_1[10].ENA
CE => TEMP_Q_1[9].ENA
CE => TEMP_Q_1[8].ENA
CE => TEMP_Q_1[7].ENA
CE => TEMP_Q_1[6].ENA
CE => TEMP_Q_1[5].ENA
CE => TEMP_Q_1[4].ENA
CE => TEMP_Q_1[3].ENA
CE => TEMP_Q_1[2].ENA
CE => TEMP_Q_1[1].ENA
CE => TEMP_Q_1[0].ENA
CLK => TEMP_Q_1[11].CLK
CLK => TEMP_Q_1[10].CLK
CLK => TEMP_Q_1[9].CLK
CLK => TEMP_Q_1[8].CLK
CLK => TEMP_Q_1[7].CLK
CLK => TEMP_Q_1[6].CLK
CLK => TEMP_Q_1[5].CLK
CLK => TEMP_Q_1[4].CLK
CLK => TEMP_Q_1[3].CLK
CLK => TEMP_Q_1[2].CLK
CLK => TEMP_Q_1[1].CLK
CLK => TEMP_Q_1[0].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
DATA[8] => TEMP_Q_1[8].DATAIN
DATA[9] => TEMP_Q_1[9].DATAIN
DATA[10] => TEMP_Q_1[10].DATAIN
DATA[11] => TEMP_Q_1[11].DATAIN
Q[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= TEMP_Q_1[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= TEMP_Q_1[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= TEMP_Q_1[10].DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= TEMP_Q_1[11].DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_and2:U8
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE


|test|generator:inst|generator_and2:U9
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE