generator_mux.vhd

sin產生器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_mux is
port (
I0 : in std_logic_vector (11 downto 0);
I1 : in std_logic_vector (11 downto 0);
S : in std_logic;
O : out std_logic_vector (11 downto 0)
);
end entity;



architecture mux_arch of generator_mux is
begin

process (S, I0)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;

end architecture;