generator_adder.vhd.bak

sin產生器

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_adder is
port (
A, B : in std_logic_vector (5 downto 0);
Q : out std_logic_vector (5 downto 0)
);
end entity;

--}} End of automatically maintained section

architecture add_anGen_arch of generator_adder is
begin

process (A, B)
begin
Q <= A + B;
end process;

end architecture add_anGen_arch;