test.tan.rpt

sin產生器

+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                         ; To                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 81.61 MHz ( period = 12.253 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[0] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.963 ns               ;
; N/A                                     ; 81.92 MHz ( period = 12.207 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[5] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.917 ns               ;
; N/A                                     ; 82.29 MHz ( period = 12.152 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[1]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.862 ns               ;
; N/A                                     ; 82.38 MHz ( period = 12.139 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[5] ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.826 ns               ;
; N/A                                     ; 82.66 MHz ( period = 12.098 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[2]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.808 ns               ;
; N/A                                     ; 82.86 MHz ( period = 12.068 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[0]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.778 ns               ;
; N/A                                     ; 83.16 MHz ( period = 12.025 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[3]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.735 ns               ;
; N/A                                     ; 83.27 MHz ( period = 12.009 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[1] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.719 ns               ;
; N/A                                     ; 83.35 MHz ( period = 11.998 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[4] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.708 ns               ;
; N/A                                     ; 83.64 MHz ( period = 11.956 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[6] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.666 ns               ;
; N/A                                     ; 83.72 MHz ( period = 11.945 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[2] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.655 ns               ;
; N/A                                     ; 84.01 MHz ( period = 11.904 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[0] ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.591 ns               ;
; N/A                                     ; 84.12 MHz ( period = 11.888 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[6] ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.575 ns               ;
; N/A                                     ; 84.30 MHz ( period = 11.862 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[3] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.572 ns               ;
; N/A                                     ; 84.40 MHz ( period = 11.849 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[7] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.559 ns               ;
; N/A                                     ; 84.46 MHz ( period = 11.840 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[4]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.550 ns               ;
; N/A                                     ; 84.72 MHz ( period = 11.803 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[1]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.490 ns               ;
; N/A                                     ; 84.85 MHz ( period = 11.785 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[8] ; generator:inst|generator_reg8:U7|TEMP_Q_1[4]  ; CLK        ; CLK      ; None                        ; None                      ; 11.495 ns               ;
; N/A                                     ; 84.88 MHz ( period = 11.781 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[7] ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.468 ns               ;
; N/A                                     ; 85.07 MHz ( period = 11.755 ns )                    ; generator:inst|generator_reg6:U1|TEMP_Q_0[5] ; generator:inst|generator_reg8:U7|TEMP_Q_1[8]  ; CLK        ; CLK      ; None                        ; None                      ; 11.449 ns               ;
; N/A                                     ; 85.11 MHz ( period = 11.749 ns )                    ; generator:inst|generator_acc6:U4|REG_Q[2]    ; generator:inst|generator_reg8:U7|TEMP_Q_1[0]  ; CLK        ; CLK      ; None                        ; None                      ; 11.436 ns               ;