generator_acc6.vhd.bak

sin產生器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_acc6 is
port (
CLK : in std_logic;
CE : in std_logic;
CLR : in std_logic;
A : in std_logic_vector (9 downto 0);
Q : out std_logic_vector (9 downto 0)
);
end entity;



architecture acc_arch of generator_acc6 is
signal REG_Q : std_logic_vector (9 downto 0);
signal TEMP_Q : std_logic_vector (9 downto 0);
begin

process (REG_Q, A)
begin
TEMP_Q <= REG_Q + A;
end process;

process(CLK, CLR)
begin
if CLR = '1' then
REG_Q <= "000000";
elsif rising_edge(CLK) then
if CE = '1' then
REG_Q <= TEMP_Q;
end if;
end if;
end process;

Q <= REG_Q;


end architecture;