generator_reg6.vhd.bak

sin產生器

library IEEE;
use IEEE.std_logic_1164.all;

entity generator_reg6 is
port (
CLR : in std_logic;
CE : in std_logic;
CLK : in std_logic;
DATA : in std_logic_vector (5 downto 0);
Q : out std_logic_vector (5 downto 0)
);
end entity;



architecture reg_arch6 of generator_reg6 is
signal TEMP_Q_0: std_logic_vector (5 downto 0);
begin

process (CLK, CLR)
begin

if CLR = '1' then
TEMP_Q_0 <= (others => '0');
elsif rising_edge(CLK) then
if CE = '1' then
TEMP_Q_0 <= DATA;
end if;
end if;

end process;

Q <= TEMP_Q_0;

end architecture;