test.tan.summary

sin產生器

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.311 ns
From           : CE
To             : generator:inst|generator_reg6:U2|TEMP_Q_0[9]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.441 ns
From           : generator:inst|generator_reg8:U7|TEMP_Q_1[7]
To             : Q[7]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.154 ns
From           : DATA[1]
To             : generator:inst|generator_reg6:U1|TEMP_Q_0[1]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 81.61 MHz ( period = 12.253 ns )
From           : generator:inst|generator_reg6:U1|TEMP_Q_0[0]
To             : generator:inst|generator_reg8:U7|TEMP_Q_1[4]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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