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LC | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC99 -> * * * | - - - - - - * * | <-- q0
LC97 -> - * * | - - - - - - * * | <-- q1
Pin
83 -> - - - | - - - - - - - - | <-- clk
1 -> - - - | - - - - - - - * | <-- reset
LC113-> - * * | - - - - - - * * | <-- a
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\homework\sjb\sjb.rpt
sjb
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC124 |LPM_ADD_SUB:62|addcore:adder|result_node3
| +----------------------------- LC122 |LPM_ADD_SUB:62|addcore:adder|result_node4
| | +--------------------------- LC121 |LPM_ADD_SUB:62|addcore:adder|result_node5
| | | +------------------------- LC116 |LPM_ADD_SUB:62|addcore:adder|result_node6
| | | | +----------------------- LC128 |LPM_ADD_SUB:62|addcore:adder|result_node7
| | | | | +--------------------- LC119 |LPM_ADD_SUB:150|addcore:adder|result_node3
| | | | | | +------------------- LC127 |LPM_ADD_SUB:150|addcore:adder|result_node4
| | | | | | | +----------------- LC126 |LPM_ADD_SUB:150|addcore:adder|result_node5
| | | | | | | | +--------------- LC125 |LPM_ADD_SUB:150|addcore:adder|result_node6
| | | | | | | | | +------------- LC114 |LPM_ADD_SUB:150|addcore:adder|result_node7
| | | | | | | | | | +----------- LC120 q3
| | | | | | | | | | | +--------- LC117 q4
| | | | | | | | | | | | +------- LC115 q5
| | | | | | | | | | | | | +----- LC118 q6
| | | | | | | | | | | | | | +--- LC123 q7
| | | | | | | | | | | | | | | +- LC113 a
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC124-> - - - - - - - - - - * - - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:62|addcore:adder|result_node3
LC122-> - - - - - - - - - - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:62|addcore:adder|result_node4
LC121-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |LPM_ADD_SUB:62|addcore:adder|result_node5
LC116-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:62|addcore:adder|result_node6
LC128-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:62|addcore:adder|result_node7
LC119-> - - - - - - - - - - * - - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:150|addcore:adder|result_node3
LC127-> - - - - - - - - - - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:150|addcore:adder|result_node4
LC126-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |LPM_ADD_SUB:150|addcore:adder|result_node5
LC125-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:150|addcore:adder|result_node6
LC114-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:150|addcore:adder|result_node7
LC120-> * * * * * * * * * * * * * * * * | - - - - - - - * | <-- q3
LC117-> - * * * * - * * * * * * * * * * | - - - - - - - * | <-- q4
LC115-> - - * * * - - * * * * * * * * * | - - - - - - - * | <-- q5
LC118-> - - - * * - - - * * * * * * * * | - - - - - - - * | <-- q6
LC123-> - - - - * - - - - * * * * * * * | - - - - - - - * | <-- q7
LC113-> - - - - - - - - - - * * * * * * | - - - - - - * * | <-- a
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
1 -> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- reset
LC99 -> * * * * * * * * * * * * * * * * | - - - - - - * * | <-- q0
LC97 -> * * * * * * * * * * * * * * * * | - - - - - - * * | <-- q1
LC101-> * * * * * * * * * * * * * * * * | - - - - - - - * | <-- q2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\homework\sjb\sjb.rpt
sjb
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':21' = 'a'
-- Equation name is 'a', location is LC113, type is buried.
a = TFFE( _EQ001, GLOBAL( clk), VCC, VCC, reset);
_EQ001 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7;
-- Node name is 'q0' = 'tmp0'
-- Equation name is 'q0', location is LC099, type is output.
q0 = TFFE( VCC, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
-- Node name is 'q1' = 'tmp1'
-- Equation name is 'q1', location is LC097, type is output.
q1 = TFFE( _EQ002, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ002 = a & !q0
# !a & q0;
-- Node name is 'q2' = 'tmp2'
-- Equation name is 'q2', location is LC101, type is output.
q2 = TFFE( _EQ003, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ003 = !a & q0 & q1
# a & !q0 & !q1;
-- Node name is 'q3' = 'tmp3'
-- Equation name is 'q3', location is LC120, type is output.
q3 = DFFE( _EQ004 $ a, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ004 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7
# a & q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6 & !q7
# !a & _LC124
# a & !_LC119;
-- Node name is 'q4' = 'tmp4'
-- Equation name is 'q4', location is LC117, type is output.
q4 = DFFE( _EQ005 $ a, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ005 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7
# a & q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6 & !q7
# !a & _LC122
# a & !_LC127;
-- Node name is 'q5' = 'tmp5'
-- Equation name is 'q5', location is LC115, type is output.
q5 = DFFE( _EQ006 $ a, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ006 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7
# a & q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6 & !q7
# !a & _LC121
# a & !_LC126;
-- Node name is 'q6' = 'tmp6'
-- Equation name is 'q6', location is LC118, type is output.
q6 = DFFE( _EQ007 $ a, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ007 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7
# a & q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6 & !q7
# !a & _LC116
# a & !_LC125;
-- Node name is 'q7' = 'tmp7'
-- Equation name is 'q7', location is LC123, type is output.
q7 = DFFE( _EQ008 $ a, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ008 = !a & !q0 & q1 & q2 & q3 & q4 & q5 & q6 & q7
# a & q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6 & !q7
# !a & _LC128
# a & !_LC114;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( q3 $ _EQ009);
_EQ009 = q0 & q1 & q2;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( q4 $ _EQ010);
_EQ010 = q0 & q1 & q2 & q3;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( q5 $ _EQ011);
_EQ011 = q0 & q1 & q2 & q3 & q4;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC116', type is buried
_LC116 = LCELL( q6 $ _EQ012);
_EQ012 = q0 & q1 & q2 & q3 & q4 & q5;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC128', type is buried
_LC128 = LCELL( q7 $ _EQ013);
_EQ013 = q0 & q1 & q2 & q3 & q4 & q5 & q6;
-- Node name is '|LPM_ADD_SUB:150|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC119', type is buried
_LC119 = LCELL( q3 $ _EQ014);
_EQ014 = !q0 & !q1 & !q2;
-- Node name is '|LPM_ADD_SUB:150|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC127', type is buried
_LC127 = LCELL( q4 $ _EQ015);
_EQ015 = !q0 & !q1 & !q2 & !q3;
-- Node name is '|LPM_ADD_SUB:150|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC126', type is buried
_LC126 = LCELL( q5 $ _EQ016);
_EQ016 = !q0 & !q1 & !q2 & !q3 & !q4;
-- Node name is '|LPM_ADD_SUB:150|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC125', type is buried
_LC125 = LCELL( q6 $ _EQ017);
_EQ017 = !q0 & !q1 & !q2 & !q3 & !q4 & !q5;
-- Node name is '|LPM_ADD_SUB:150|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC114', type is buried
_LC114 = LCELL( q7 $ _EQ018);
_EQ018 = !q0 & !q1 & !q2 & !q3 & !q4 & !q5 & !q6;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\homework\sjb\sjb.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,202K
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