sjb.fit

FPGA或CPLD与DAC（DAC0832）

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 10/16/2007 16:24:40      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "sjb"
BEGIN

    DEVICE = "EPM7128SLI84-10";

    "clk"                          : INPUT_PIN  = 83     ;
    "reset"                        : INPUT_PIN  = 1      ;
    "q0"                           : OUTPUT_PIN = 64     ; -- LC99
    "q1"                           : OUTPUT_PIN = 63     ; -- LC97
    "q2"                           : OUTPUT_PIN = 65     ; -- LC101
    "q3"                           : OUTPUT_PIN = 76     ; -- LC120
    "q4"                           : OUTPUT_PIN = 74     ; -- LC117
    "q5"                           : OUTPUT_PIN = 73     ; -- LC115
    "q6"                           : OUTPUT_PIN = 75     ; -- LC118
    "q7"                           : OUTPUT_PIN = 77     ; -- LC123
    "|LPM_ADD_SUB:62|addcore:adder|result_node3" : LOCATION   = LC124  ;
    "|LPM_ADD_SUB:62|addcore:adder|result_node4" : LOCATION   = LC122  ;
    "|LPM_ADD_SUB:62|addcore:adder|result_node5" : LOCATION   = LC121  ;
    "|LPM_ADD_SUB:62|addcore:adder|result_node6" : LOCATION   = LC116  ;
    "|LPM_ADD_SUB:62|addcore:adder|result_node7" : LOCATION   = LC128  ; -- PIN 81
    "|LPM_ADD_SUB:150|addcore:adder|result_node3" : LOCATION   = LC119  ;
    "|LPM_ADD_SUB:150|addcore:adder|result_node4" : LOCATION   = LC127  ;
    "|LPM_ADD_SUB:150|addcore:adder|result_node5" : LOCATION   = LC126  ; -- PIN 80
    "|LPM_ADD_SUB:150|addcore:adder|result_node6" : LOCATION   = LC125  ; -- PIN 79
    "|LPM_ADD_SUB:150|addcore:adder|result_node7" : LOCATION   = LC114  ;
    ":21"                          : LOCATION   = LC113  ;  -- a

END;

INTERNAL_INFO "sjb"
BEGIN
	DEVICE = EPM7128SLI84-10;
	LC123   : LORAX = "G144R0,PA18R0C7";
	LC118   : LORAX = "G111R0,PA14R0C7";
	LC115   : LORAX = "G55R0,PA3R0C7";
	LC117   : LORAX = "G110R0,PA17R0C7";
	LC120   : LORAX = "G113R0,PA10R0C7";
	LC101   : LORAX = "G49R0,PA2R0C7";
	LC97    : LORAX = "G106R0,PA11R0C6,PA11R0C7";
	LC99    : LORAX = "G108R0,PA12R0C6,PA16R0C7";
	OH130R0P1 : LORAX = "G81R0,PA9R0C7";
	LC113   : LORAX = "G53R0,PA7R0C6,PA7R0C7";
	LC128   : LORAX = "G202R0,PA31R0C7";
	LC114   : LORAX = "G54R0,PA5R0C7";
	LC116   : LORAX = "G56R0,PA1R0C7";
	LC125   : LORAX = "G199R0,PA28R0C7";
	LC121   : LORAX = "G142R0,PA19R0C7";
	LC126   : LORAX = "G200R0,PA32R0C7";
	LC122   : LORAX = "G143R0,PA23R0C7";
	LC127   : LORAX = "G201R0,PA27R0C7";
	LC124   : LORAX = "G145R0,PA22R0C7";
	LC119   : LORAX = "G112R0,PA12R0C7";
END;