a.v

来自「这个程序是用VHDL语言编写的对AD7862在数据采集中进行设计」· Verilog 代码 · 共 19 行

module adc(clk,rst,convst,busy_adc);
input clk,rst,convst;
inout busy_adc;
reg busy_adcbuf;
assign busy_adc=busy_adcbuf;
always@(posedge clk or negedge rst)
  begin
   if(!rst)busy_adcbuf<=0;
   else
    if(!convst)
     begin
      busy_adcbuf=1;
      end
   if(busy_adcbuf)
    begin
      #110 busy_adcbuf=0;
     end
   end
endmodule