ad.v

来自「这个程序是用VHDL语言编写的对AD7862在数据采集中进行设计」· Verilog 代码 · 共 74 行

module fsm1(rst,clk,convst,busy_adc,a0_adc,cs_adc,rd_adc,out);
output a0_adc,cs_adc,rd_adc,out;
input clk,rst,busy_adc,convst;
reg cs_adc,rd_adc;
reg a0_adc=0;
reg[2:0] state;
reg[3:0] out;
parameter ready=3'h0,start=3'h1,waiting=3'h2,read1=3'h3,read2=3'h4,read3=3'h5;
always@(posedge clk or negedge rst or negedge convst)
  begin
   if(!rst)
    begin
     a0_adc=0;
     cs_adc=1;
     rd_adc=1;
     state=ready;
    end
   else
    begin
     case(state)
      ready:if(!convst)
       begin
        state=start;
       end
      else
        state=ready;
     start:if(busy_adc)
       begin
        state=waiting;
       end
      else
        state=start;
     waiting:if(!busy_adc)
        begin
        cs_adc<=0;
        rd_adc<=0;
        state<=read1;
        end
       else
        state=waiting;
     read1:fork
        #10cs_adc=1;
        #10rd_adc=1;
        #10state=read2;
       join
     read2:fork
        #10cs_adc=0;
        #10rd_adc=0;
        #10state=read3;
        #20a0_adc=~a0_adc;
       join
     read3:fork
        #20cs_adc=1;
        #20rd_adc=1;
        #30state=ready;
       join
     default:begin
        a0_adc=0;
        cs_adc=1;
        rd_adc=1;
        #20state=ready;
       end
     endcase
    end
   end
always@(rd_adc)
  begin
   if(rd_adc==0)
    out=4'b0011;  
   else
    out=4'bzzzz;
  end
adc myadc(clk,rst,convst,busy_adc);  
endmodule