dspcompress.txt

Quartus ii下dspcompress的文件

library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY DSPCompress IS
	PORT ( 
	-- General Signal 
		nReset				: IN STD_LOGIC;
		CPLDCLK    		: IN STD_LOGIC;  -- 50MHz
		-- DSP Interface Signal								
		nCE1,nCE2,nAOE ,nARE			: IN STD_LOGIC;
		GIO0,GIO1,TOUT0,TOUT1		: IN STD_LOGIC;	
		DMAC1,DMAC2					: IN STD_LOGIC;
		IACK							: IN STD_LOGIC;
		ODD_INT,EVEN_INT				: OUT STD_LOGIC;
		INT6,INT7,NMI					: OUT STD_LOGIC;
		TIN0,TIN1						: OUT STD_LOGIC;
		nDSP2LSD						: OUT STD_LOGIC;
		-- SAA7114H Interface Signal 	
		LCLK,LLC							: IN STD_LOGIC;
			IGPH,IGPV,IGP0,IGP1,IDQ			: IN STD_LOGIC;
		RTS0,RTS1							: IN STD_LOGIC;
       ITRDY								: OUT STD_LOGIC;
		
			-- FIFOs Interface Signal
       	FIFO_WCK							: OUT STD_LOGIC;
        	nFIFO_WE,nFIFO_WRST				: OUT STD_LOGIC;
       nFIFO_RE,nFIFO_OE,nFIFO_RRST	: OUT STD_LOGIC
		);
END DSPCompress;			
ARCHITECTURE Behavior Of DSPCompress IS
TYPE RStateType IS (RIdle,Read,ReadPause,ReadEnd);	 
TYPE WStateType IS (Init,WIdle,R1Pixel,R2Pixel,SkipPixel,_
RLineEnd,DSPINT,FieldEnd);
SIGNAL	RState							: RStateType;
SIGNAL	WState							: WStateType;
SIGNAL	OddField						: STD_LOGIC;				
-- delay signal
SIGNAL	nFIFO_RRST_P,nFIFO_RRST_P1		: STD_LOGIC;
SIGNAL nFIFO_OE_P,nFIFO_OE_P1			: STD_LOGIC;
SIGNAL	nFIFO_WE_P,nFIFO_WRST_P			: STD_LOGIC;	
SIGNAL ODD_INT_P,EVEN_INT_P				: STD_LOGIC;
SIGNAL	nFIFO_WE_P1,nFIFO_WRST_P1		: STD_LOGIC;	
SIGNAL ODD_INT_P1,EVEN_INT_P1			: STD_LOGIC;
-- delay cell
COMPONENT LCELL
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;
begin
	--pull up DSP interrupt signal
	NMI <= '1';
	INT6 <= '1';
	TIN0 <= '0';
	TIN1 <= '0';
 	INT7 <= '1';
	-- EMIF data bus buffer direction 
	nDSP2LSD <= nCE1 and nCE2; 
	-- FIFOs write clock
	FIFO_WCK <= LCLK;
	ITRDY <= '1';
-- FIFO Read control 
P1:process(CPLDCLK,nReset)
begin
	if nReset = '0' then
		RState <= ReadEnd;
	elsif CPLDCLK'event and CPLDCLK = '0' then
		case RState is
			when RIdle => 
				if nCE2 = '0' and GIO0 = '0' and nAOE = '0' then
					RState <= Read;
				end if;					
			when Read => 
				if nCE2 = '1' and GIO0 = '0' then
					RState <= ReadPause;
				end if;
			when ReadPause =>
				if GIO0 = '1' then
					RState <= ReadEnd;
				elsif nCE2 = '0' and nAOE = '0' then
					RState <= Read;
				end if;
			when ReadEnd =>
				RState <= RIdle;
		end case;
	end if;
end process;
P2:process(RState)
begin
	case RState is
		when RIdle => 
		nFIFO_RE <= '1';
			nFIFO_OE_P <= '1';
			nFIFO_RRST_P <= '1';
		when Read => 
			nFIFO_RE <= '0';
			nFIFO_OE_P <= '0';
		when ReadPause =>	
			nFIFO_RE <= '1';
			nFIFO_OE_P <= '0';
		when ReadEnd =>	  
			nFIFO_OE_P <= '1'; 
			nFIFO_RE <= '1';
			nFIFO_RRST_P <= '0';
	end case;		
end process;		
P3:process(LCLK,nReset)
begin
	if nReset = '0' then
		WState <= Init;
	elsif LCLK'event and LCLK = '1' then
		case WState is
			when WIdle => 
				if IGPH = '1' then
					WState <= R1Pixel;
				end if;
			when R1Pixel =>
				if IGPH = '0' then
					WState <= RLineEnd;
				else
					WState <= R2Pixel;
				end if;
			when R2Pixel =>
				WState <= SkipPixel;
			when SkipPixel =>	  
				WState <= R1Pixel;
			when RLineEnd =>
				if IGPV = '0' then
					WState <= DSPINT;
				elsif IGPH = '1' then
					WState <= R1Pixel;
				else
					WState <= RLineEnd;
				end if;
			when DSPINT =>  
				WState <= FieldEnd;
			when FieldEnd =>   
				WState <= WIdle;
			when Init =>
				WState <= WIdle;
		end case;
	end if;
end process;
P4:process(WState)
begin				  
	case WState is
		when WIdle => 
			nFIFO_WE_P <= '1';
			nFIFO_WRST_P <= '1';
			ODD_INT_P <= '1';
			EVEN_INT_P <= '1';
		when R1Pixel =>	   
	  		nFIFO_WE_P <= '1';
		when R2Pixel =>		
			nFIFO_WE_P <= '0';
		when SkipPixel =>	
			nFIFO_WE_P <= '0';
		when RLineEnd =>	
			nFIFO_WE_P <= '1';
		when DSPINT =>	
			nFIFO_WE_P <= '1';	
			if OddField = '1' then
				ODD_INT_P <= '0';
				EVEN_INT_P <= '1';
			else
				EVEN_INT_P <= '0';
				ODD_INT_P <= '1';
			end if;
		when FieldEnd => 
			ODD_INT_P <= '1';
			EVEN_INT_P <= '1';
			nFIFO_WRST_P <= '0';
		when Init =>	   
			nFIFO_WE_P <= '1';
			nFIFO_WRST_P <= '0';
			ODD_INT_P <= '1';
			EVEN_INT_P <= '1';
	end case;		
end process;		
P5:process(RTS1,nReset)
begin
	-- RTS0 -> HREF
	-- RTS1 -> V123	 
	if nReset = '0' then
		OddField <= '1';
	elsif RTS1'event and RTS1 = '0' then
		OddField <= RTS0;
	end if;	
end process; 
-- delay lcell
Udalay0:LCELL port map (nFIFO_RRST_P,nFIFO_RRST_P1);
Udelay1:LCELL port map (nFIFO_OE_P,nFIFO_OE_P1);
Udelay2:LCELL port map (nFIFO_WE_P,nFIFO_WE_P1);
Udelay3:LCELL port map (nFIFO_WRST_P,nFIFO_WRST_P1);
Udelay4:LCELL port map (ODD_INT_P,ODD_INT_P1);
Udelay5:LCELL port map (EVEN_INT_P,EVEN_INT_P1);
Udelay6:LCELL port map (nFIFO_RRST_P1,nFIFO_RRST);
Udelay7:LCELL port map (nFIFO_OE_P1,nFIFO_OE);
Udelay8:LCELL port map (nFIFO_WE_P1,nFIFO_WE);
Udelay9:LCELL port map (nFIFO_WRST_P1,nFIFO_WRST);
Udelay10:LCELL port map (ODD_INT_P1,ODD_INT);
Udelay11:LCELL port map (EVEN_INT_P1,EVEN_INT);
END Behavior;