vga.map.qmsg

用Verilog做的VGA 480X640彩色驱动

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 18 20:21:27 2004 " "Info: Processing started: Sat Dec 18 20:21:27 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off vga -c vga " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off vga -c vga" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga.v 1 1 " "Info: Found 1 design units and 1 entities in source file vga.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "vga" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "pxl_cnt\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: pxl_cnt\[0\]~0" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "pxl_cnt\[0\]~0" { Text "F:/work/vga680x480_color_bar01/vga.v" 58 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "ln_cnt\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: ln_cnt\[0\]~0" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "ln_cnt\[0\]~0" { Text "F:/work/vga680x480_color_bar01/vga.v" 82 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 233 -1 0 } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 233 -1 0 } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 273 -1 0 } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 273 -1 0 } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 253 -1 0 } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 253 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "106 " "Info: Implemented 106 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "6 " "Info: Implemented 6 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 18 20:21:30 2004 " "Info: Processing ended: Sat Dec 18 20:21:30 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}