vga.tan.qmsg

用Verilog做的VGA 480X640彩色驱动

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register g_cnt\[1\] register b_cnt\[0\] 64.94 MHz 15.4 ns Internal " "Info: Clock clk has Internal fmax of 64.94 MHz between source register g_cnt\[1\] and destination register b_cnt\[0\] (period= 15.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest register register " "Info: + Longest register to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns g_cnt\[1\] 1 REG LC8_F2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_F2; Fanout = 9; REG Node = 'g_cnt\[1\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { g_cnt[1] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 173 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns i~8 2 COMB LC2_F2 2 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC2_F2; Fanout = 2; COMB Node = 'i~8'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "1.900 ns" { g_cnt[1] i~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 4.400 ns i165~2 3 COMB LC1_F1 6 " "Info: 3: + IC(0.900 ns) + CELL(1.600 ns) = 4.400 ns; Loc. = LC1_F1; Fanout = 6; COMB Node = 'i165~2'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.500 ns" { i~8 i165~2 } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 177 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 7.600 ns i192~46 4 COMB LC3_D1 2 " "Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 7.600 ns; Loc. = LC3_D1; Fanout = 2; COMB Node = 'i192~46'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "3.200 ns" { i165~2 i192~46 } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 197 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 9.600 ns i238~92 5 COMB LC8_D1 4 " "Info: 5: + IC(0.300 ns) + CELL(1.700 ns) = 9.600 ns; Loc. = LC8_D1; Fanout = 4; COMB Node = 'i238~92'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.000 ns" { i192~46 i238~92 } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 218 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 11.300 ns i243~27 6 COMB LC5_D1 3 " "Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 11.300 ns; Loc. = LC5_D1; Fanout = 3; COMB Node = 'i243~27'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "1.700 ns" { i238~92 i243~27 } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 225 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 13.200 ns i251~0 7 COMB LC6_D1 1 " "Info: 7: + IC(0.300 ns) + CELL(1.600 ns) = 13.200 ns; Loc. = LC6_D1; Fanout = 1; COMB Node = 'i251~0'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "1.900 ns" { i243~27 i251~0 } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 223 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 14.300 ns b_cnt\[0\] 8 REG LC7_D1 6 " "Info: 8: + IC(0.300 ns) + CELL(0.800 ns) = 14.300 ns; Loc. = LC7_D1; Fanout = 6; REG Node = 'b_cnt\[0\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "1.100 ns" { i251~0 b_cnt[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 221 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.100 ns 70.63 % " "Info: Total cell delay = 10.100 ns ( 70.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns 29.37 % " "Info: Total interconnect delay = 4.200 ns ( 29.37 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "14.300 ns" { g_cnt[1] i~8 i165~2 i192~46 i238~92 i243~27 i251~0 b_cnt[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 52 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 52; CLK Node = 'clk'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns b_cnt\[0\] 2 REG LC7_D1 6 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_D1; Fanout = 6; REG Node = 'b_cnt\[0\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "0.400 ns" { clk b_cnt[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 221 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk b_cnt[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 52 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 52; CLK Node = 'clk'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns g_cnt\[1\] 2 REG LC8_F2 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_F2; Fanout = 9; REG Node = 'g_cnt\[1\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "0.400 ns" { clk g_cnt[1] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 173 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk g_cnt[1] } "NODE_NAME" } } }  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk b_cnt[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk g_cnt[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 173 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 221 -1 0 } }  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "14.300 ns" { g_cnt[1] i~8 i165~2 i192~46 i238~92 i243~27 i251~0 b_cnt[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk b_cnt[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk g_cnt[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk r\[1\] r_reg\[2\] 11.900 ns register " "Info: tco from clock clk to destination pin r\[1\] through register r_reg\[2\] is 11.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 52 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 52; CLK Node = 'clk'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns r_reg\[2\] 2 REG LC1_F10 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F10; Fanout = 1; REG Node = 'r_reg\[2\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "0.400 ns" { clk r_reg[2] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 253 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk r_reg[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 253 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register pin " "Info: + Longest register to pin delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns r_reg\[2\] 1 REG LC1_F10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F10; Fanout = 1; REG Node = 'r_reg\[2\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { r_reg[2] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 253 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(4.800 ns) 9.000 ns r\[1\] 2 PIN Pin_44 0 " "Info: 2: + IC(4.200 ns) + CELL(4.800 ns) = 9.000 ns; Loc. = Pin_44; Fanout = 0; PIN Node = 'r\[1\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "9.000 ns" { r_reg[2] r[1] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns 53.33 % " "Info: Total cell delay = 4.800 ns ( 53.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns 46.67 % " "Info: Total interconnect delay = 4.200 ns ( 46.67 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "9.000 ns" { r_reg[2] r[1] } "NODE_NAME" } } }  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk r_reg[2] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "9.000 ns" { r_reg[2] r[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk g\[0\] g_reg\[3\] 9.900 ns register " "Info: Minimum tco from clock clk to destination pin g\[0\] through register g_reg\[3\] is 9.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 52 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 52; CLK Node = 'clk'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns g_reg\[3\] 2 REG LC1_F27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F27; Fanout = 1; REG Node = 'g_reg\[3\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "0.400 ns" { clk g_reg[3] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 233 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk g_reg[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 233 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns g_reg\[3\] 1 REG LC1_F27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F27; Fanout = 1; REG Node = 'g_reg\[3\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "" { g_reg[3] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 233 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(4.800 ns) 7.000 ns g\[0\] 2 PIN Pin_38 0 " "Info: 2: + IC(2.200 ns) + CELL(4.800 ns) = 7.000 ns; Loc. = Pin_38; Fanout = 0; PIN Node = 'g\[0\]'" {  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "7.000 ns" { g_reg[3] g[0] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/vga.v" "" "" { Text "F:/work/vga680x480_color_bar01/vga.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns 68.57 % " "Info: Total cell delay = 4.800 ns ( 68.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 31.43 % " "Info: Total interconnect delay = 2.200 ns ( 31.43 % )" {  } {  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "7.000 ns" { g_reg[3] g[0] } "NODE_NAME" } } }  } 0}  } { { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "2.400 ns" { clk g_reg[3] } "NODE_NAME" } } } { "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" "" "" { Report "F:/work/vga680x480_color_bar01/db/vga_cmp.qrpt" Compiler "vga" "UNKNOWN" "V1" "F:/work/vga680x480_color_bar01/db/vga.quartus_db" { Floorplan "" "" "7.000 ns" { g_reg[3] g[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 18 20:21:49 2004 " "Info: Processing ended: Sat Dec 18 20:21:49 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}