vga.map.eqn

用Verilog做的VGA 480X640彩色驱动

--r_reg[3] is r_reg[3]
--operation mode is normal

r_reg[3]_lut_out = !r_cnt[2] & !r_cnt[0] & r_cnt[1] & A1L63;
r_reg[3] = DFFEA(r_reg[3]_lut_out, clk, !rst, , , , );


--h_active is h_active
--operation mode is normal

h_active_lut_out = C2L62 # h_active & (C2_q[4] # !A1L96);
h_active = DFFEA(h_active_lut_out, clk, !rst, , , , );


--v_active is v_active
--operation mode is normal

v_active_lut_out = A1L53 # C1_q[5] & C1L42;
v_active = DFFEA(v_active_lut_out, clk, !rst, , , , );


--A1L63 is i112~50
--operation mode is normal

A1L63 = h_active & v_active;


--g_cnt[0] is g_cnt[0]
--operation mode is normal

g_cnt[0]_lut_out = A1L64 # A1L46 & A1L34 & !A1L73;
g_cnt[0] = DFFEA(g_cnt[0]_lut_out, clk, !rst, , , , );


--g_cnt[2] is g_cnt[2]
--operation mode is normal

g_cnt[2]_lut_out = !A1L73 & (A1L44 # g_cnt[2] & A1L54);
g_cnt[2] = DFFEA(g_cnt[2]_lut_out, clk, !rst, , , , );


--g_cnt[1] is g_cnt[1]
--operation mode is normal

g_cnt[1]_lut_out = A1L04 & A1L14 & !A1L73;
g_cnt[1] = DFFEA(g_cnt[1]_lut_out, clk, !rst, , , , );


--b_cnt[0] is b_cnt[0]
--operation mode is normal

b_cnt[0]_lut_out = !A1L36 & (b_cnt[0] $ A1L06);
b_cnt[0] = DFFEA(b_cnt[0]_lut_out, clk, !rst, , , , );


--b_cnt[2] is b_cnt[2]
--operation mode is normal

b_cnt[2]_lut_out = !A1L73 & (b_cnt[2] & !A1L26 # !b_cnt[2] & b_cnt[1] & A1L26);
b_cnt[2] = DFFEA(b_cnt[2]_lut_out, clk, !rst, , , , );


--b_cnt[1] is b_cnt[1]
--operation mode is normal

b_cnt[1]_lut_out = !A1L73 & (b_cnt[1] & !A1L26 # !b_cnt[1] & !b_cnt[2] & A1L26);
b_cnt[1] = DFFEA(b_cnt[1]_lut_out, clk, !rst, , , , );


--A1L16 is i243~26
--operation mode is normal

A1L16 = b_cnt[2] & !b_cnt[1];


--r_cnt[0] is r_cnt[0]
--operation mode is normal

r_cnt[0]_lut_out = A1L95 & (video_act_dly # !v_active # !h_active);
r_cnt[0] = DFFEA(r_cnt[0]_lut_out, clk, !rst, , , , );


--r_cnt[2] is r_cnt[2]
--operation mode is normal

r_cnt[2]_lut_out = !A1L55;
r_cnt[2] = DFFEA(r_cnt[2]_lut_out, clk, !rst, , , , );


--r_cnt[1] is r_cnt[1]
--operation mode is normal

r_cnt[1]_lut_out = !A1L85;
r_cnt[1] = DFFEA(r_cnt[1]_lut_out, clk, !rst, , , , );


--C2L62 is lpm_counter:pxl_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~325
--operation mode is normal

C2L62 = C2L42 & C2_q[7] & !C2_q[4] & !C2_q[6];


--A1L96 is ln_end~44
--operation mode is normal

A1L96 = C2_q[0] & C2L32 & A1L86;


--A1L53 is i103~0
--operation mode is normal

A1L53 = v_active & (!C1_q[1] # !A1L43 # !C1L32);


--step[1] is step[1]
--operation mode is normal

step[1]_lut_out = step[0] & !step[1] & !A1L73;
step[1] = DFFEA(step[1]_lut_out, clk, !rst, , , , );


--step[0] is step[0]
--operation mode is normal

step[0]_lut_out = !step[0] & !A1L73 & !step[1];
step[0] = DFFEA(step[0]_lut_out, clk, !rst, , , , );


--A1L24 is i167~291
--operation mode is normal

A1L24 = step[1] & !step[0];


--g_dir is g_dir
--operation mode is normal

g_dir_lut_out = !A1L93 & (video_act_dly # !v_active # !h_active);
g_dir = DFFEA(g_dir_lut_out, clk, !rst, , , , );


--A1L56 is i~8
--operation mode is normal

A1L56 = !g_cnt[1] & !g_cnt[0] & !g_cnt[2];


--i136 is i136
--operation mode is normal

i136 = g_dir & A1L56 & step[1] & !step[0];


--video_act_dly is video_act_dly
--operation mode is normal

video_act_dly_lut_out = h_active & v_active;
video_act_dly = DFFEA(video_act_dly_lut_out, clk, !rst, , , , );


--A1L73 is i117~32
--operation mode is normal

A1L73 = h_active & v_active & !video_act_dly;


--A1L64 is i169~189
--operation mode is normal

A1L64 = !i136 & !A1L73 & (g_cnt[0] $ A1L24);


--A1L46 is i~7
--operation mode is normal

A1L46 = g_cnt[0] & g_cnt[2] & !g_cnt[1];


--A1L34 is i167~292
--operation mode is normal

A1L34 = step[1] & !g_dir & !step[0];


--A1L44 is i167~293
--operation mode is normal

A1L44 = g_cnt[0] & g_cnt[1] & A1L34 & !g_cnt[2];


--A1L54 is i167~294
--operation mode is normal

A1L54 = g_dir & (g_cnt[0] # g_cnt[1]) # !g_dir & (!g_cnt[1] # !g_cnt[0]) # !A1L24;


--A1L04 is i159~211
--operation mode is normal

A1L04 = g_cnt[1] $ (A1L24 & (g_cnt[0] $ g_dir));


--A1L14 is i165~2
--operation mode is normal

A1L14 = g_dir & !A1L56 # !g_dir & !A1L46 # !A1L24;


--A1L84 is i192~46
--operation mode is normal

A1L84 = !r_cnt[1] & !A1L14;


--r_dir is r_dir
--operation mode is normal

r_dir_lut_out = !A1L73 & (A1L74 # r_dir & !A1L94);
r_dir = DFFEA(r_dir_lut_out, clk, !rst, , , , );


--A1L06 is i238~92
--operation mode is normal

A1L06 = A1L84 & (r_cnt[0] & r_cnt[2] & !r_dir # !r_cnt[0] & !r_cnt[2] & r_dir);


--A1L26 is i243~27
--operation mode is normal

A1L26 = b_cnt[0] & A1L06;


--A1L36 is i251~0
--operation mode is normal

A1L36 = A1L73 # A1L26 & b_cnt[2] & !b_cnt[1];


--A1L05 is i207~24
--operation mode is normal

A1L05 = !A1L14 & !r_dir;


--A1L74 is i189~37
--operation mode is normal

A1L74 = r_cnt[0] & r_cnt[2] & A1L05 & !r_cnt[1];


--A1L94 is i192~47
--operation mode is normal

A1L94 = r_dir & A1L84 & !r_cnt[0] & !r_cnt[2];


--A1L95 is i225~109
--operation mode is normal

A1L95 = A1L74 # !A1L94 & (r_cnt[0] $ !A1L14);


--A1L93 is i139~48
--operation mode is normal

A1L93 = g_dir & i136 # !g_dir & (!A1L24 # !A1L46);


--i209 is i209
--operation mode is normal

i209 = r_dir & !A1L14;


--A1L25 is i223~384
--operation mode is normal

A1L25 = r_cnt[2] $ (!r_cnt[0] & !r_cnt[1] & i209);


--A1L35 is i223~385
--operation mode is normal

A1L35 = A1L05 # A1L73 # A1L94 # !A1L25;


--A1L45 is i223~386
--operation mode is normal

A1L45 = A1L05 & (r_cnt[2] $ (r_cnt[0] & r_cnt[1]));


--A1L55 is i223~388
--operation mode is normal

A1L55 = (A1L73 # !A1L74 & (A1L94 # !A1L45)) & CASCADE(A1L35);


--A1L65 is i224~233
--operation mode is normal

A1L65 = r_cnt[1] $ (!r_cnt[0] & !A1L14 & r_dir);


--A1L75 is i224~234
--operation mode is normal

A1L75 = A1L05 # A1L73 # A1L06 # !A1L65;


--A1L66 is i~84
--operation mode is normal

A1L66 = r_cnt[0] $ r_cnt[1];


--A1L85 is i224~236
--operation mode is normal

A1L85 = (A1L73 # A1L06 # !A1L05 # !A1L66) & CASCADE(A1L75);


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--hs is hs
--operation mode is output

hs = OUTPUT(hs_r);


--vs is vs
--operation mode is output

vs = OUTPUT(vs_r);


--g[1] is g[1]
--operation mode is bidir

g[1]_tri_out = TRI(g_reg[0], !g_reg[2]);
g[1] = BIDIR(g[1]_tri_out);


--g[0] is g[0]
--operation mode is bidir

g[0]_tri_out = TRI(g_reg[1], !g_reg[3]);
g[0] = BIDIR(g[0]_tri_out);


--b[1] is b[1]
--operation mode is bidir

b[1]_tri_out = TRI(b_reg[0], !b_reg[2]);
b[1] = BIDIR(b[1]_tri_out);


--b[0] is b[0]
--operation mode is bidir

b[0]_tri_out = TRI(b_reg[1], !b_reg[3]);
b[0] = BIDIR(b[0]_tri_out);


--r[1] is r[1]
--operation mode is bidir

r[1]_tri_out = TRI(r_reg[0], !r_reg[2]);
r[1] = BIDIR(r[1]_tri_out);


--r[0] is r[0]
--operation mode is bidir

r[0]_tri_out = TRI(r_reg[1], !r_reg[3]);
r[0] = BIDIR(r[0]_tri_out);