vga.v

用Verilog做的VGA 480X640彩色驱动

module vga(
    rst,
    clk,
    hs,
    vs,
    g,
    b,
    r
);

input           rst;
input           clk;
output          hs;
output          vs;
inout   [1:0]   g;
inout   [1:0]   b;
inout   [1:0]   r;

reg     [9:0]   pxl_cnt;
reg     [9:0]   ln_cnt;
reg             hs_r;
reg             vs_r;

reg     [3:0]   g_reg;
reg     [2:0]   g_cnt;
reg     [3:0]   r_reg;
reg     [2:0]   r_cnt;
reg     [3:0]   b_reg;
reg     [2:0]   b_cnt;

reg             g_dir;
reg             r_dir;
wire            r_cnt_en;
wire            b_cnt_en;

reg     [1:0]   step;

reg             h_active;
reg             v_active;

wire            ln_end;
wire            frm_end;
wire            hsync_end;
wire            vsync_end;
wire            h_act_start;
wire            h_act_end;
wire            v_act_start;
wire            v_act_end;

wire            video_active;

assign  ln_end=(pxl_cnt==10'd793) ? 1'b1 : 1'b0;
assign  hsync_end=(pxl_cnt==10'd89) ? 1'b1 : 1'b0;
assign  h_act_start=(pxl_cnt==10'd137) ? 1'b1 : 1'b0;
assign  h_act_end=(pxl_cnt==10'd777) ? 1'b1 : 1'b0;

always @ (posedge clk or posedge rst)
    if (rst)
        pxl_cnt<=10'h000;
    else if(ln_end)
        pxl_cnt<=10'h000;
    else
        pxl_cnt<=pxl_cnt+1'b1;
        
always @ (posedge clk or posedge rst)
    if (rst)
        h_active<=1'b0;
    else if (h_act_start)
        h_active<=1'b1;
    else if (h_act_end)
        h_active<=1'b0;    
    else        
        h_active<=h_active;
        
        
assign  frm_end=(ln_cnt==10'd524 && ln_end) ? 1'b1 : 1'b0;
assign  vsync_end=(ln_cnt==10'd01 && ln_end) ? 1'b1 : 1'b0;
assign  v_act_start=(ln_cnt==10'd33 && ln_end) ? 1'b1 : 1'b0;
assign  v_act_end=(ln_cnt==10'd514 && ln_end) ? 1'b1 : 1'b0;

always @ (posedge clk or posedge rst)
    if (rst)
        ln_cnt<=10'h000;
    else if(frm_end)
        ln_cnt<=10'h000;
    else if (ln_end)
        ln_cnt<=ln_cnt+1'b1;
    else
        ln_cnt<=ln_cnt;    
        
always @ (posedge clk or posedge rst)
    if (rst)
        v_active<=1'b0;
    else if (v_act_start)
        v_active<=1'b1;
    else if (v_act_end)
        v_active<=1'b0;
    else
        v_active<=v_active;        
       
always @ (posedge clk or posedge rst)
    if (rst)
        hs_r<=1'b0;    
    else if (hsync_end)
        hs_r<=1'b1;        
    else if(ln_end)
        hs_r<=1'b0;    
    else 
        hs_r<=hs_r;
        
always @ (posedge clk or posedge rst)
    if (rst)
        vs_r<=1'b0;    
    else if (vsync_end)
        vs_r<=1'b1;        
    else if(frm_end)
        vs_r<=1'b0;    
    else 
        vs_r<=vs_r;

assign  video_active=h_active & v_active;
        
assign  hs=hs_r;
assign  vs=vs_r;
/*
assign  r=(video_active) ? pxl_cnt[1:0] : 2'b00;
assign  g=(video_active) ? pxl_cnt[3:2] : 2'b00;
assign  b=(video_active) ? pxl_cnt[5:4] : 2'b00;
*/
/*
assign  r=(video_active) ? {pxl_cnt[4],pxl_cnt[3]} : 2'b00;
assign  g=(video_active) ? {pxl_cnt[6],pxl_cnt[5]} : 2'b00;
assign  b=(video_active) ? {pxl_cnt[8],pxl_cnt[7]} : 2'b00;
*/

wire     g_cnt_en;
reg      video_act_dly;
wire     video_act_rise;

always @ (posedge clk or posedge rst)
    if (rst)
        video_act_dly<=1'b0;
    else
        video_act_dly<=video_active;

assign video_act_rise=video_active & ~video_act_dly;


assign g_cnt_en=(step==2'b10) ? 1'b1 :1'b0;
always @ (posedge clk or posedge rst)
    if (rst)
        step<=2'b00;
    else if(video_act_rise)
        step<=2'b00;    
    else if(g_cnt_en)
        step<=2'b00;
    else
        step<=step+1'b1;

always @ (posedge clk or posedge rst)
    if (rst)
        g_dir<=1'b0;
    else if (video_act_rise)
        g_dir<=1'b0;
    else if (g_cnt==3'b101 && g_cnt_en && ~g_dir)
        g_dir<=1'b1;
    else if (g_cnt==3'b000 && g_cnt_en && g_dir)
        g_dir<=1'b0;
    else
        g_dir<=g_dir;    
        
always @ (posedge clk or posedge rst)
    if (rst)
        g_cnt<=3'b000;
    else if (video_act_rise)
        g_cnt<=3'b000;
    else if (g_cnt==3'b101 && g_cnt_en && ~g_dir)
        g_cnt<=3'b101;
    else if (g_cnt==3'b000 && g_cnt_en && g_dir)
        g_cnt<=3'b000;
    else if (g_cnt_en && ~g_dir)
        g_cnt<=g_cnt+1'b1;
    else if (g_cnt_en && g_dir)
        g_cnt<=g_cnt-1'b1;    
    else
        g_cnt<=g_cnt;

assign  r_cnt_en=((g_cnt==3'b101) && g_cnt_en && ~g_dir || (g_cnt==3'b000) && g_cnt_en && g_dir ) ? 1'b1 :1'b0;

always @ (posedge clk or posedge rst)
    if (rst)
        r_dir<=1'b0;
    else if (video_act_rise)
        r_dir<=1'b0;
    else if (r_cnt==3'b101 && r_cnt_en && ~r_dir)
        r_dir<=1'b1;
    else if (r_cnt==3'b000 && r_cnt_en && r_dir)
        r_dir<=1'b0;
    else
        r_dir<=r_dir;

always @ (posedge clk or posedge rst)
    if (rst)
        r_cnt<=3'b000;
    else if (video_act_rise)
        r_cnt<=3'b000;
    else if (r_cnt==3'b101 && r_cnt_en && ~r_dir)
        r_cnt<=3'b101;
    else if (r_cnt==3'b000 && r_cnt_en && r_dir)
        r_cnt<=3'b000;
    else if (r_cnt_en && ~r_dir)
        r_cnt<=r_cnt+1'b1;
    else if (r_cnt_en && r_dir)
        r_cnt<=r_cnt-1'b1;    
    else
        r_cnt<=r_cnt;

assign  b_cnt_en=((r_cnt==3'b101) && r_cnt_en && ~r_dir || (r_cnt==3'b000) && r_cnt_en && r_dir ) ? 1'b1 :1'b0;

always @ (posedge clk or posedge rst)
    if (rst)
        b_cnt<=3'b000;
    else if (video_act_rise)
        b_cnt<=3'b000;
    else if (b_cnt==3'b101 && b_cnt_en)
        b_cnt<=3'b000;
    else if (b_cnt_en)
        b_cnt<=b_cnt+1'b1;
    else
        b_cnt<=b_cnt;
        
always @ (posedge clk or posedge rst)
    if(rst)
        g_reg<=4'b1100;
    else if(~video_active)
        g_reg<=4'b1100;
    else begin
        case (g_cnt)
            3'b000 : g_reg<=4'b1100;
            3'b001 : g_reg<=4'b1101;
            3'b010 : g_reg<=4'b0101;
            3'b011 : g_reg<=4'b1110;
            3'b100 : g_reg<=4'b1010;
            3'b101 : g_reg<=4'b1111;
            default: g_reg<=4'b1100;           
        endcase
    end

assign g[1]=(g_reg[2]) ? g_reg[0] : 1'bz;
assign g[0]=(g_reg[3]) ? g_reg[1] : 1'bz;

always @ (posedge clk or posedge rst)
    if(rst)
        r_reg<=4'b1100;
    else if(~video_active)
        r_reg<=4'b1100;
    else begin
        case (r_cnt)
            3'b000 : r_reg<=4'b1100;
            3'b001 : r_reg<=4'b1101;
            3'b010 : r_reg<=4'b0101;
            3'b011 : r_reg<=4'b1110;
            3'b100 : r_reg<=4'b1010;
            3'b101 : r_reg<=4'b1111;
            default: r_reg<=4'b1100;           
        endcase
    end

assign r[1]=(r_reg[2]) ? r_reg[0] : 1'bz;
assign r[0]=(r_reg[3]) ? r_reg[1] : 1'bz;

always @ (posedge clk or posedge rst)
    if(rst)
        b_reg<=4'b1100;
    else if(~video_active)
        b_reg<=4'b1100;
    else begin
        case (b_cnt)
            3'b000 : b_reg<=4'b1100;
            3'b001 : b_reg<=4'b1101;
            3'b010 : b_reg<=4'b0101;
            3'b011 : b_reg<=4'b1110;
            3'b100 : b_reg<=4'b1010;
            3'b101 : b_reg<=4'b1111;
            default: b_reg<=4'b1100;           
        endcase
    end

assign b[1]=(b_reg[2]) ? b_reg[0] : 1'bz;
assign b[0]=(b_reg[3]) ? b_reg[1] : 1'bz;

endmodule