key0.tan.qmsg

VHDL接口电路实用源程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:div_cnt_rtl_0\|dffs\[20\] register key_code\[3\] 71.43 MHz 14.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 71.43 MHz between source register \"lpm_counter:div_cnt_rtl_0\|dffs\[20\]\" and destination register \"key_code\[3\]\" (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[20\] 1 REG LC36 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 13; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[20\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns Mux~1763 2 COMB LC51 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC51; Fanout = 1; COMB Node = 'Mux~1763'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "8.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] Mux~1763 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns key_code\[3\] 3 REG LC52 30 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC52; Fanout = 30; REG Node = 'key_code\[3\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "1.000 ns" { Mux~1763 key_code[3] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] Mux~1763 key_code[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] Mux~1763 key_code[3] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { clk } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns key_code\[3\] 2 REG LC52 30 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC52; Fanout = 30; REG Node = 'key_code\[3\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "0.000 ns" { clk key_code[3] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { clk } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:div_cnt_rtl_0\|dffs\[20\] 2 REG LC36 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 13; REG Node = 'lpm_counter:div_cnt_rtl_0\|dffs\[20\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "0.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] Mux~1763 key_code[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { lpm_counter:div_cnt_rtl_0|dffs[20] Mux~1763 key_code[3] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk lpm_counter:div_cnt_rtl_0|dffs[20] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:div_cnt_rtl_0|dffs[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "key_code\[2\] column\[2\] clk 12.000 ns register " "Info: tsu for register \"key_code\[2\]\" (data pin = \"column\[2\]\", clock pin = \"clk\") is 12.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns column\[2\] 1 PIN PIN_37 24 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'column\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { column[2] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns Mux~1759 2 COMB LC49 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC49; Fanout = 1; COMB Node = 'Mux~1759'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "8.000 ns" { column[2] Mux~1759 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns key_code\[2\] 3 REG LC50 31 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC50; Fanout = 31; REG Node = 'key_code\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "1.000 ns" { Mux~1759 key_code[2] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 81.82 % " "Info: Total cell delay = 9.000 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 18.18 % " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "11.000 ns" { column[2] Mux~1759 key_code[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { column[2] column[2]~out Mux~1759 key_code[2] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { clk } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns key_code\[2\] 2 REG LC50 31 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC50; Fanout = 31; REG Node = 'key_code\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "0.000 ns" { clk key_code[2] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "11.000 ns" { column[2] Mux~1759 key_code[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { column[2] column[2]~out Mux~1759 key_code[2] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}