serial.map.eqn

VHDL接口电路实用源程序

A1L241_p4_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & state_tras[1] & state_tras[3] & !txd_buf[3] & state_tras[2] & state_tras[0] & !send_state[2] & send_state[0];
A1L241 = A1L141 # A1L241_p0_out # A1L241_p1_out # A1L241_p2_out # A1L241_p3_out # A1L241_p4_out;


--A1L341 is txd_buf[3]~587
A1L341_p0_out = key_entry2 & txd_buf[3] & !txd_buf[4] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & !state_tras[1] & !state_tras[2];
A1L341_p1_out = key_entry1 & !key_entry2 & txd_buf[3];
A1L341_p2_out = key_entry2 & txd_buf[3] & !txd_buf[4] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0] & !state_tras[3];
A1L341_p3_out = key_entry2 & txd_buf[3] & !txd_buf[4] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[3] & state_tras[1];
A1L341_p4_out = key_entry2 & txd_buf[3] & !txd_buf[4] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[3] & state_tras[2];
A1L341 = A1L241 # A1L341_p0_out # A1L341_p1_out # A1L341_p2_out # A1L341_p3_out # A1L341_p4_out;


--A1L731 is txd_buf[2]~593
A1L731_p1_out = !div8_tras_reg[1] & txd_buf[2];
A1L731_p2_out = txd_buf[2] & !div8_tras_reg[0];
A1L731_p3_out = txd_buf[2] & !div8_tras_reg[2];
A1L731_p4_out = txd_buf[2] & !state_tras[2] & txd_buf[3];
A1L731 = A1L731_p1_out # A1L731_p2_out # A1L731_p3_out # A1L731_p4_out;


--A1L831 is txd_buf[2]~598
A1L831_p0_out = state_tras[0] & state_tras[3] & !state_tras[1] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[2];
A1L831_p1_out = !send_state[1] & txd_buf[3] & txd_buf[2];
A1L831_p2_out = txd_buf[2] & state_tras[0] & state_tras[3] & !state_tras[1];
A1L831_p3_out = !send_state[1] & state_tras[0] & state_tras[3] & state_tras[1] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[2];
A1L831_p4_out = state_tras[0] & state_tras[3] & state_tras[1] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[2] & send_state[0] & !send_state[2];
A1L831 = A1L731 # A1L831_p0_out # A1L831_p1_out # A1L831_p2_out # A1L831_p3_out # A1L831_p4_out;


--A1L931 is txd_buf[2]~604
A1L931_p0_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[2] & txd_buf[3] & !state_tras[3];
A1L931_p1_out = !key_entry2 & key_entry1;
A1L931_p2_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[0] & !state_tras[1] & !state_tras[2] & txd_buf[3];
A1L931_p3_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[1] & !state_tras[2] & txd_buf[3] & state_tras[3];
A1L931_p4_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[1] & txd_buf[3] & !state_tras[3];
A1L931 = A1L831 # A1L931_p0_out # A1L931_p1_out # A1L931_p2_out # A1L931_p3_out # A1L931_p4_out;


--A1L531 is txd_buf[1]~610
A1L531_p0_out = !state_tras[0] & txd_buf[1] & !state_tras[3] & !state_tras[1] & !state_tras[2];
A1L531_p1_out = !state_tras[0] & txd_buf[1] & txd_buf[2];
A1L531_p2_out = state_tras[0] & !send_state[2] & send_state[1] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & state_tras[1] & state_tras[2];
A1L531_p3_out = !state_tras[0] & txd_buf[2] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & !state_tras[1] & !state_tras[2];
A1L531_p4_out = txd_buf[1] & state_tras[3] & !state_tras[1] & state_tras[2];
A1L531 = A1L531_p0_out # A1L531_p1_out # A1L531_p2_out # A1L531_p3_out # A1L531_p4_out;


--A1L231 is txd_buf[0]~616
A1L231_p1_out = send_state[1] & !send_state[2] & key_entry2 & state_tras[0] & state_tras[3] & state_tras[1] & state_tras[2] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L231 = A1L231_p1_out;


--A1L331 is txd_buf[0]~618
A1L331_p0_out = state_tras[0] & state_tras[3] & state_tras[1] & state_tras[2] & key_entry2 & A1L031 & !send_state[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L331_p1_out = txd_buf[0] & !state_tras[0] & !state_tras[3] & !state_tras[1] & !state_tras[2];
A1L331_p2_out = txd_buf[0] & A1L821 & A1L56;
A1L331_p3_out = !state_tras[3] & A1L941 & txd_buf[1] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L331_p4_out = state_tras[3] & !state_tras[1] & !state_tras[2] & key_entry2 & A1L921 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L331 = A1L231 # A1L331_p0_out # A1L331_p1_out # A1L331_p2_out # A1L331_p3_out # A1L331_p4_out;


--A1L651 is txd_reg~69
A1L651_p1_out = !state_tras[1] & !txd_buf[0] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & !state_tras[2] & !state_tras[0];
A1L651_p2_out = !state_tras[1] & !state_tras[3] & !state_tras[2] & !state_tras[0] & !txd_reg;
A1L651_p3_out = !txd_reg & A1L841;
A1L651 = A1L651_p1_out # A1L651_p2_out # A1L651_p3_out;


--~GND~9 is ~GND~9
~GND~9_or_out = GND;
~GND~9 = ~GND~9_or_out;


--~GND~10 is ~GND~10
~GND~10_or_out = GND;
~GND~10 = ~GND~10_or_out;


--~GND~11 is ~GND~11
~GND~11_or_out = GND;
~GND~11 = ~GND~11_or_out;


--~GND~12 is ~GND~12
~GND~12_or_out = GND;
~GND~12 = ~GND~12_or_out;


--~GND~13 is ~GND~13
~GND~13_or_out = GND;
~GND~13 = ~GND~13_or_out;


--~GND~14 is ~GND~14
~GND~14_or_out = GND;
~GND~14 = ~GND~14_or_out;


--~GND~15 is ~GND~15
~GND~15_or_out = GND;
~GND~15 = ~GND~15_or_out;


--~GND~16 is ~GND~16
~GND~16_or_out = GND;
~GND~16 = ~GND~16_or_out;


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~GND~17 is ~GND~17
~GND~17_or_out = GND;
~GND~17 = ~GND~17_or_out;


--A1L46 is reduce_nor~133sexp
A1L46 = EXP(div_reg[1] & div_reg[0] & !div_reg[13] & !div_reg[15] & !div_reg[12] & div_reg[8] & !div_reg[3] & !div_reg[10] & !div_reg[4] & !div_reg[5] & !div_reg[2] & !div_reg[9] & !div_reg[6] & !div_reg[7] & !div_reg[11] & !div_reg[14]);


--A1L56 is reduce_nor~136sexp
A1L56 = EXP(div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1]);


--A1L321 is trasstart~50bal
A1L321_p1_out = send_state[0] & send_state[2] & send_state[1];
A1L321_or_out = A1L321_p1_out;
A1L321 = !(A1L321_or_out);


--rst is rst
--operation mode is input

rst = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--key_input is key_input
--operation mode is input

key_input = INPUT();


--rxd is rxd
--operation mode is input

rxd = INPUT();


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(~GND~9);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(~GND~10);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(~GND~11);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(~GND~12);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(~GND~13);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(~GND~14);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(~GND~15);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(~GND~16);


--seg_data[0] is seg_data[0]
--operation mode is output

seg_data[0] = OUTPUT(~VCC~1);


--lowbit is lowbit
--operation mode is output

lowbit = OUTPUT(~GND~17);


--seg_data[3] is seg_data[3]
--operation mode is output

seg_data[3] = OUTPUT(A1L66);


--seg_data[2] is seg_data[2]
--operation mode is output

seg_data[2] = OUTPUT(A1L86);


--seg_data[1] is seg_data[1]
--operation mode is output

seg_data[1] = OUTPUT(A1L07);


--seg_data[4] is seg_data[4]
--operation mode is output

seg_data[4] = OUTPUT(A1L27);


--seg_data[5] is seg_data[5]
--operation mode is output

seg_data[5] = OUTPUT(A1L37);


--seg_data[6] is seg_data[6]
--operation mode is output

seg_data[6] = OUTPUT(A1L57);


--seg_data[7] is seg_data[7]
--operation mode is output

seg_data[7] = OUTPUT(A1L67);


--txd is txd
--operation mode is output

txd = OUTPUT(txd_reg);