来自「VHDL硬件描述语言的一系列例子」· 代码 · 共 27 行

-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn 

Library IEEE ;
use IEEE.std_logic_1164.all ;


ENTITY condsigm IS
	PORT
	(
		high, mid, low	: IN  BIT;
		q				: OUT INTEGER
	);
END condsigm;

ARCHITECTURE maxpld OF condsigm IS
BEGIN

q <=	3 WHEN high = '1' ELSE	-- when high
		2 WHEN mid  = '1' ELSE	-- when mid but not high
		1 WHEN low  = '1' ELSE	-- when low but not mid or high
		0;						-- when not low, mid, or high
		
END maxpld;