div.map.qmsg

div的verilog开发程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 16:26:49 2007 " "Info: Processing started: Fri Jun 15 16:26:49 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off div -c div " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div -c div" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "touch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file touch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 touch-rtl " "Info: Found design unit 1: touch-rtl" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 touch " "Info: Found entity 1: touch" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/杨华/程序/div/div1246.vhd " "Warning: Can't analyze file -- file F:/杨华/程序/div/div1246.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div1248.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div1248.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div1248-rtl " "Info: Found design unit 1: div1248-rtl" {  } { { "div1248.vhd" "" { Text "F:/杨华/程序/div/div1248.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div1248 " "Info: Found entity 1: div1248" {  } { { "div1248.vhd" "" { Text "F:/杨华/程序/div/div1248.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file div.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div2_4_8_16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div2_4_8_16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div2_4_8_16-rtl " "Info: Found design unit 1: div2_4_8_16-rtl" {  } { { "div2_4_8_16.vhd" "" { Text "F:/杨华/程序/div/div2_4_8_16.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div2_4_8_16 " "Info: Found entity 1: div2_4_8_16" {  } { { "div2_4_8_16.vhd" "" { Text "F:/杨华/程序/div/div2_4_8_16.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "div " "Info: Elaborating entity \"div\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "div2_4_8_16 inst5 " "Warning: Block or symbol \"div2_4_8_16\" of instance \"inst5\" overlaps another block or symbol" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 80 392 504 208 "inst5" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out2 " "Warning: Pin \"out2\" is missing source" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 488 664 120 "out2" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out4 " "Warning: Pin \"out4\" is missing source" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 120 488 664 136 "out4" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out8 " "Warning: Pin \"out8\" is missing source" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 136 488 664 152 "out8" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out16 " "Warning: Pin \"out16\" is missing source" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 152 488 664 168 "out16" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch touch:inst4 " "Info: Elaborating entity \"touch\" for hierarchy \"touch:inst4\"" {  } { { "div.bdf" "inst4" { Schematic "F:/杨华/程序/div/div.bdf" { { 64 224 344 160 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div2_4_8_16 div2_4_8_16:inst5 " "Info: Elaborating entity \"div2_4_8_16\" for hierarchy \"div2_4_8_16:inst5\"" {  } { { "div.bdf" "inst5" { Schematic "F:/杨华/程序/div/div.bdf" { { 80 392 504 208 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out2 GND " "Warning: Pin \"out2\" stuck at GND" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 488 664 120 "out2" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out4 GND " "Warning: Pin \"out4\" stuck at GND" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 120 488 664 136 "out4" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out8 GND " "Warning: Pin \"out8\" stuck at GND" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 136 488 664 152 "out8" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out16 GND " "Warning: Pin \"out16\" stuck at GND" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 152 488 664 168 "out16" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "6 " "Info: Implemented 6 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 16:26:52 2007 " "Info: Processing ended: Fri Jun 15 16:26:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}