sigdata.v

Verilog源码

`timescale 1ns/1ns
module sigdata(sclk,data,d_ena);
output d_ena;
output[3:0] data;
output sclk;
reg sclk,d_ena;
reg[3:0] data;
reg[7:0] count;

initial
   begin
      sclk=0;
      d_ena=0;
      data=0; 
      count=0;
  end
  
always #50 sclk=~sclk;

always @(posedge sclk)
   begin
      count=count+1;
         if(count==8)
            begin
               d_ena=~d_ena;
               count=0;
           end
       end
       
always @(posedge d_ena)
   begin
      #(100*8) data=data+1;
  end
endmodule