a8255.map.rpt

8255的vhdl 程序

; A8255.vhd                        ; yes             ; User VHDL File  ; G:/FPGA/8255_OSED/A8255.vhd    ;
+----------------------------------+-----------------+-----------------+--------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 184       ;
; Total combinational functions   ; 146       ;
;     -- Total 4-input functions  ; 97        ;
;     -- Total 3-input functions  ; 26        ;
;     -- Total 2-input functions  ; 19        ;
;     -- Total 1-input functions  ; 4         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 54        ;
; I/O pins                        ; 81        ;
; Maximum fan-out node            ; CLK       ;
; Maximum fan-out                 ; 54        ;
; Total fan-out                   ; 743       ;
; Average fan-out                 ; 2.80      ;
+---------------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name        ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; |a8255                     ; 184 (0)     ; 54           ; 0           ; 81   ; 0            ; 130 (0)      ; 38 (0)            ; 16 (0)           ; 0 (0)           ; 0 (0)      ; |a8255                     ;
;    |cntl_log:I_cntl_log|   ; 37 (37)     ; 7            ; 0           ; 0    ; 0            ; 30 (30)      ; 3 (3)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |a8255|cntl_log:I_cntl_log ;
;    |dout_mux:I_dout_mux|   ; 35 (35)     ; 0            ; 0           ; 0    ; 0            ; 35 (35)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8255|dout_mux:I_dout_mux ;
;    |portain:I_portain|     ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8255|portain:I_portain   ;
;    |portaout:I_portaout|   ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8255|portaout:I_portaout ;
;    |portbin:I_portbin|     ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8255|portbin:I_portbin   ;
;    |portbout:I_portbout|   ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8255|portbout:I_portbout ;
;    |portcout:I_portcout|   ; 80 (80)     ; 15           ; 0           ; 0    ; 0            ; 65 (65)      ; 3 (3)             ; 12 (12)          ; 0 (0)           ; 0 (0)      ; |a8255|portcout:I_portcout ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 54    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 54    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 39    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; cntl_log:I_cntl_log|ControlRegQ[0]     ; 4       ;
; cntl_log:I_cntl_log|ControlRegQ[1]     ; 6       ;
; cntl_log:I_cntl_log|ControlRegQ[3]     ; 5       ;
; cntl_log:I_cntl_log|ControlRegQ[4]     ; 13      ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Sep 11 19:52:34 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255
Info: Found 2 design units, including 1 entities, in source file CNTL_LOG.VHD
    Info: Found design unit 1: cntl_log-rtl
    Info: Found entity 1: cntl_log
Info: Found 2 design units, including 1 entities, in source file DOUT_MUX.VHD
    Info: Found design unit 1: dout_mux-rtl
    Info: Found entity 1: dout_mux
Info: Found 2 design units, including 1 entities, in source file PORTAIN.VHD
    Info: Found design unit 1: portain-rtl
    Info: Found entity 1: portain
Info: Found 2 design units, including 1 entities, in source file PORTAOUT.VHD
    Info: Found design unit 1: portaout-rtl
    Info: Found entity 1: portaout
Info: Found 2 design units, including 1 entities, in source file PORTBIN.VHD
    Info: Found design unit 1: portbin-rtl
    Info: Found entity 1: portbin
Info: Found 2 design units, including 1 entities, in source file PORTBOUT.VHD
    Info: Found design unit 1: portbout-rtl
    Info: Found entity 1: portbout
Info: Found 2 design units, including 1 entities, in source file PORTCOUT.VHD
    Info: Found design unit 1: portcout-rtl
    Info: Found entity 1: portcout
Info: Found 2 design units, including 1 entities, in source file A8255.vhd
    Info: Found design unit 1: a8255-structure
    Info: Found entity 1: a8255
Info: Elaborating entity "A8255" for the top level hierarchy
Info: Elaborating entity "dout_mux" for hierarchy "dout_mux:I_dout_mux"
Warning (10005): Verilog HDL or VHDL warning at DOUT_MUX.VHD(22): sensitivity list already contains DOUTSelect
Info: Elaborating entity "cntl_log" for hierarchy "cntl_log:I_cntl_log"
Info: Elaborating entity "portaout" for hierarchy "portaout:I_portaout"
Info: Elaborating entity "portain" for hierarchy "portain:I_portain"
Info: Elaborating entity "portbout" for hierarchy "portbout:I_portbout"
Info: Elaborating entity "portbin" for hierarchy "portbin:I_portbin"
Info: Elaborating entity "portcout" for hierarchy "portcout:I_portcout"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 265 device resources after synthesis - the final resource count might be different
    Info: Implemented 39 input pins
    Info: Implemented 42 output pins
    Info: Implemented 184 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Sep 11 19:52:47 2007
    Info: Elapsed time: 00:00:13