a8255.map.qmsg

8255的vhdl 程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 12 21:53:43 2007 " "Info: Processing started: Wed Sep 12 21:53:43 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255 --generate_inc_file=G:\\FPGA\\8255_OSED\\A8255.tcl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255 --generate_inc_file=G:\\FPGA\\8255_OSED\\A8255.tcl" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "ESGN_NON_DESIGN_FILE" "G:\\FPGA\\8255_OSED\\A8255.tcl " "Error: File G:\\FPGA\\8255_OSED\\A8255.tcl is not a recognized design file type" {  } {  } 0 0 "File %1!s! is not a recognized design file type" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Sep 12 21:53:44 2007 " "Error: Processing ended: Wed Sep 12 21:53:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}