a8255.tan.qmsg

8255的vhdl 程序

{ "Info" "ITDB_TH_RESULT" "portain:I_portain\|PortAInRegQ\[0\] PAIN\[0\] CLK -2.348 ns register " "Info: th for register \"portain:I_portain\|PortAInRegQ\[0\]\" (data pin = \"PAIN\[0\]\", clock pin = \"CLK\") is -2.348 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.668 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.000 ns) 1.668 ns portain:I_portain\|PortAInRegQ\[0\] 2 REG LC3_1_F2 1 " "Info: 2: + IC(0.778 ns) + CELL(0.000 ns) = 1.668 ns; Loc. = LC3_1_F2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { CLK portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "PORTAIN.VHD" "" { Text "G:/FPGA/8255_OSED/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.36 % ) " "Info: Total cell delay = 0.890 ns ( 53.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.778 ns ( 46.64 % ) " "Info: Total interconnect delay = 0.778 ns ( 46.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.668 ns" { CLK portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.668 ns" { CLK CLK~out0 portain:I_portain|PortAInRegQ[0] } { 0.000ns 0.000ns 0.778ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "PORTAIN.VHD" "" { Text "G:/FPGA/8255_OSED/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.380 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns PAIN\[0\] 1 PIN PIN_35 2 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_35; Fanout = 2; PIN Node = 'PAIN\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PAIN[0] } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.061 ns) + CELL(0.079 ns) 4.380 ns portain:I_portain\|PortAInRegQ\[0\] 2 REG LC3_1_F2 1 " "Info: 2: + IC(3.061 ns) + CELL(0.079 ns) = 4.380 ns; Loc. = LC3_1_F2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.140 ns" { PAIN[0] portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "PORTAIN.VHD" "" { Text "G:/FPGA/8255_OSED/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 30.11 % ) " "Info: Total cell delay = 1.319 ns ( 30.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.061 ns ( 69.89 % ) " "Info: Total interconnect delay = 3.061 ns ( 69.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.380 ns" { PAIN[0] portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.380 ns" { PAIN[0] PAIN[0]~out0 portain:I_portain|PortAInRegQ[0] } { 0.000ns 0.000ns 3.061ns } { 0.000ns 1.240ns 0.079ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.668 ns" { CLK portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.668 ns" { CLK CLK~out0 portain:I_portain|PortAInRegQ[0] } { 0.000ns 0.000ns 0.778ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.380 ns" { PAIN[0] portain:I_portain|PortAInRegQ[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.380 ns" { PAIN[0] PAIN[0]~out0 portain:I_portain|PortAInRegQ[0] } { 0.000ns 0.000ns 3.061ns } { 0.000ns 1.240ns 0.079ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 11 19:53:21 2007 " "Info: Processing ended: Tue Sep 11 19:53:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}