a8255.tan.qmsg

8255的vhdl 程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register cntl_log:I_cntl_log\|ControlRegQ\[6\] register portcout:I_portcout\|PortCOutRegQ\[3\] 183.12 MHz 5.461 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 183.12 MHz between source register \"cntl_log:I_cntl_log\|ControlRegQ\[6\]\" and destination register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (period= 5.461 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.928 ns + Longest register register " "Info: + Longest register to register delay is 4.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 1 REG LC6_9_A2 20 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_9_A2; Fanout = 20; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.879 ns) 1.388 ns portcout:I_portcout\|PortCOutRegD\[3\]~7085 2 COMB LC3_8_A2 6 " "Info: 2: + IC(0.348 ns) + CELL(0.879 ns) = 1.388 ns; Loc. = LC3_8_A2; Fanout = 6; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~7085'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.227 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.798 ns) 3.336 ns portcout:I_portcout\|PortCOutRegD\[3\]~7101 3 COMB LC2_4_A2 1 " "Info: 3: + IC(1.150 ns) + CELL(0.798 ns) = 3.336 ns; Loc. = LC2_4_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~7101'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.948 ns" { portcout:I_portcout|PortCOutRegD[3]~7085 portcout:I_portcout|PortCOutRegD[3]~7101 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.531 ns) 4.928 ns portcout:I_portcout\|PortCOutRegQ\[3\] 4 REG LC8_2_A2 7 " "Info: 4: + IC(1.061 ns) + CELL(0.531 ns) = 4.928 ns; Loc. = LC8_2_A2; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.592 ns" { portcout:I_portcout|PortCOutRegD[3]~7101 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.369 ns ( 48.07 % ) " "Info: Total cell delay = 2.369 ns ( 48.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.559 ns ( 51.93 % ) " "Info: Total interconnect delay = 2.559 ns ( 51.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.928 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 portcout:I_portcout|PortCOutRegD[3]~7101 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.928 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 portcout:I_portcout|PortCOutRegD[3]~7101 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.348ns 1.150ns 1.061ns } { 0.161ns 0.879ns 0.798ns 0.531ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.673 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns portcout:I_portcout\|PortCOutRegQ\[3\] 2 REG LC8_2_A2 7 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC8_2_A2; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.673 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 2 REG LC6_9_A2 20 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC6_9_A2; Fanout = 20; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.928 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 portcout:I_portcout|PortCOutRegD[3]~7101 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.928 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 portcout:I_portcout|PortCOutRegD[3]~7101 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.348ns 1.150ns 1.061ns } { 0.161ns 0.879ns 0.798ns 0.531ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[3] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "portcout:I_portcout\|PortCOutRegQ\[5\] A\[1\] CLK 11.117 ns register " "Info: tsu for register \"portcout:I_portcout\|PortCOutRegQ\[5\]\" (data pin = \"A\[1\]\", clock pin = \"CLK\") is 11.117 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.592 ns + Longest pin register " "Info: + Longest pin to register delay is 12.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns A\[1\] 1 PIN PIN_14 27 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_14; Fanout = 27; PIN Node = 'A\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { A[1] } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.890 ns) 6.019 ns cntl_log:I_cntl_log\|ControlLogicProc~71 2 COMB LC3_9_A2 12 " "Info: 2: + IC(3.889 ns) + CELL(0.890 ns) = 6.019 ns; Loc. = LC3_9_A2; Fanout = 12; COMB Node = 'cntl_log:I_cntl_log\|ControlLogicProc~71'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.779 ns" { A[1] cntl_log:I_cntl_log|ControlLogicProc~71 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.733 ns) + CELL(0.890 ns) 8.642 ns cntl_log:I_cntl_log\|PortCOutLd\[1\]~825 3 COMB LC3_5_F2 2 " "Info: 3: + IC(1.733 ns) + CELL(0.890 ns) = 8.642 ns; Loc. = LC3_5_F2; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[1\]~825'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.623 ns" { cntl_log:I_cntl_log|ControlLogicProc~71 cntl_log:I_cntl_log|PortCOutLd[1]~825 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.890 ns) 11.183 ns cntl_log:I_cntl_log\|PortCOutLd\[5\]~829 4 COMB LC9_5_A2 2 " "Info: 4: + IC(1.651 ns) + CELL(0.890 ns) = 11.183 ns; Loc. = LC9_5_A2; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[5\]~829'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.541 ns" { cntl_log:I_cntl_log|PortCOutLd[1]~825 cntl_log:I_cntl_log|PortCOutLd[5]~829 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.358 ns) 11.787 ns portcout:I_portcout\|PortCOutRegD~7114 5 COMB LC9_4_A2 1 " "Info: 5: + IC(0.246 ns) + CELL(0.358 ns) = 11.787 ns; Loc. = LC9_4_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD~7114'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.604 ns" { cntl_log:I_cntl_log|PortCOutLd[5]~829 portcout:I_portcout|PortCOutRegD~7114 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.531 ns) 12.592 ns portcout:I_portcout\|PortCOutRegQ\[5\] 6 REG LC10_4_A2 6 " "Info: 6: + IC(0.274 ns) + CELL(0.531 ns) = 12.592 ns; Loc. = LC10_4_A2; Fanout = 6; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.805 ns" { portcout:I_portcout|PortCOutRegD~7114 portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.799 ns ( 38.11 % ) " "Info: Total cell delay = 4.799 ns ( 38.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.793 ns ( 61.89 % ) " "Info: Total interconnect delay = 7.793 ns ( 61.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.592 ns" { A[1] cntl_log:I_cntl_log|ControlLogicProc~71 cntl_log:I_cntl_log|PortCOutLd[1]~825 cntl_log:I_cntl_log|PortCOutLd[5]~829 portcout:I_portcout|PortCOutRegD~7114 portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.592 ns" { A[1] A[1]~out0 cntl_log:I_cntl_log|ControlLogicProc~71 cntl_log:I_cntl_log|PortCOutLd[1]~825 cntl_log:I_cntl_log|PortCOutLd[5]~829 portcout:I_portcout|PortCOutRegD~7114 portcout:I_portcout|PortCOutRegQ[5] } { 0.000ns 0.000ns 3.889ns 1.733ns 1.651ns 0.246ns 0.274ns } { 0.000ns 1.240ns 0.890ns 0.890ns 0.890ns 0.358ns 0.531ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.673 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns portcout:I_portcout\|PortCOutRegQ\[5\] 2 REG LC10_4_A2 6 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC10_4_A2; Fanout = 6; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[5] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.592 ns" { A[1] cntl_log:I_cntl_log|ControlLogicProc~71 cntl_log:I_cntl_log|PortCOutLd[1]~825 cntl_log:I_cntl_log|PortCOutLd[5]~829 portcout:I_portcout|PortCOutRegD~7114 portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.592 ns" { A[1] A[1]~out0 cntl_log:I_cntl_log|ControlLogicProc~71 cntl_log:I_cntl_log|PortCOutLd[1]~825 cntl_log:I_cntl_log|PortCOutLd[5]~829 portcout:I_portcout|PortCOutRegD~7114 portcout:I_portcout|PortCOutRegQ[5] } { 0.000ns 0.000ns 3.889ns 1.733ns 1.651ns 0.246ns 0.274ns } { 0.000ns 1.240ns 0.890ns 0.890ns 0.890ns 0.358ns 0.531ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 portcout:I_portcout|PortCOutRegQ[5] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[7\] cntl_log:I_cntl_log\|ControlRegQ\[6\] 14.763 ns register " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[7\]\" through register \"cntl_log:I_cntl_log\|ControlRegQ\[6\]\" is 14.763 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.673 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 2 REG LC6_9_A2 20 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC6_9_A2; Fanout = 20; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.755 ns + Longest register pin " "Info: + Longest register to pin delay is 12.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 1 REG LC6_9_A2 20 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_9_A2; Fanout = 20; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.879 ns) 1.388 ns portcout:I_portcout\|PortCOutRegD\[3\]~7085 2 COMB LC3_8_A2 6 " "Info: 2: + IC(0.348 ns) + CELL(0.879 ns) = 1.388 ns; Loc. = LC3_8_A2; Fanout = 6; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~7085'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.227 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "G:/FPGA/8255_OSED/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.358 ns) 2.892 ns cntl_log:I_cntl_log\|Mux0~86 3 COMB LC1_3_A2 16 " "Info: 3: + IC(1.146 ns) + CELL(0.358 ns) = 2.892 ns; Loc. = LC1_3_A2; Fanout = 16; COMB Node = 'cntl_log:I_cntl_log\|Mux0~86'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.504 ns" { portcout:I_portcout|PortCOutRegD[3]~7085 cntl_log:I_cntl_log|Mux0~86 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.731 ns) + CELL(0.879 ns) 5.502 ns dout_mux:I_dout_mux\|Mux0~75 4 COMB LC9_1_E2 1 " "Info: 4: + IC(1.731 ns) + CELL(0.879 ns) = 5.502 ns; Loc. = LC9_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~75'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.610 ns" { cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.879 ns) 7.379 ns dout_mux:I_dout_mux\|Mux0~76 5 COMB LC7_2_E2 1 " "Info: 5: + IC(0.998 ns) + CELL(0.879 ns) = 7.379 ns; Loc. = LC7_2_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~76'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.358 ns) 8.004 ns dout_mux:I_dout_mux\|Mux0~77 6 COMB LC5_1_E2 1 " "Info: 6: + IC(0.267 ns) + CELL(0.358 ns) = 8.004 ns; Loc. = LC5_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~77'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.625 ns" { dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.341 ns) + CELL(2.410 ns) 12.755 ns DOUT\[7\] 7 PIN PIN_79 0 " "Info: 7: + IC(2.341 ns) + CELL(2.410 ns) = 12.755 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'DOUT\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.751 ns" { dout_mux:I_dout_mux|Mux0~77 DOUT[7] } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.924 ns ( 46.44 % ) " "Info: Total cell delay = 5.924 ns ( 46.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.831 ns ( 53.56 % ) " "Info: Total interconnect delay = 6.831 ns ( 53.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.755 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.755 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } { 0.000ns 0.348ns 1.146ns 1.731ns 0.998ns 0.267ns 2.341ns } { 0.161ns 0.879ns 0.358ns 0.879ns 0.879ns 0.358ns 2.410ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.673 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.755 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.755 ns" { cntl_log:I_cntl_log|ControlRegQ[6] portcout:I_portcout|PortCOutRegD[3]~7085 cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } { 0.000ns 0.348ns 1.146ns 1.731ns 0.998ns 0.267ns 2.341ns } { 0.161ns 0.879ns 0.358ns 0.879ns 0.879ns 0.358ns 2.410ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] DOUT\[7\] 15.727 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"DOUT\[7\]\" is 15.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns A\[0\] 1 PIN PIN_8 41 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_8; Fanout = 41; PIN Node = 'A\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.745 ns) + CELL(0.879 ns) 5.864 ns cntl_log:I_cntl_log\|Mux0~86 2 COMB LC1_3_A2 16 " "Info: 2: + IC(3.745 ns) + CELL(0.879 ns) = 5.864 ns; Loc. = LC1_3_A2; Fanout = 16; COMB Node = 'cntl_log:I_cntl_log\|Mux0~86'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.624 ns" { A[0] cntl_log:I_cntl_log|Mux0~86 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "G:/FPGA/8255_OSED/CNTL_LOG.VHD" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.731 ns) + CELL(0.879 ns) 8.474 ns dout_mux:I_dout_mux\|Mux0~75 3 COMB LC9_1_E2 1 " "Info: 3: + IC(1.731 ns) + CELL(0.879 ns) = 8.474 ns; Loc. = LC9_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~75'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.610 ns" { cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.879 ns) 10.351 ns dout_mux:I_dout_mux\|Mux0~76 4 COMB LC7_2_E2 1 " "Info: 4: + IC(0.998 ns) + CELL(0.879 ns) = 10.351 ns; Loc. = LC7_2_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~76'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.358 ns) 10.976 ns dout_mux:I_dout_mux\|Mux0~77 5 COMB LC5_1_E2 1 " "Info: 5: + IC(0.267 ns) + CELL(0.358 ns) = 10.976 ns; Loc. = LC5_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux0~77'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.625 ns" { dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "G:/FPGA/8255_OSED/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.341 ns) + CELL(2.410 ns) 15.727 ns DOUT\[7\] 6 PIN PIN_79 0 " "Info: 6: + IC(2.341 ns) + CELL(2.410 ns) = 15.727 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'DOUT\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.751 ns" { dout_mux:I_dout_mux|Mux0~77 DOUT[7] } "NODE_NAME" } } { "A8255.vhd" "" { Text "G:/FPGA/8255_OSED/A8255.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.645 ns ( 42.25 % ) " "Info: Total cell delay = 6.645 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.082 ns ( 57.75 % ) " "Info: Total interconnect delay = 9.082 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.727 ns" { A[0] cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.727 ns" { A[0] A[0]~out0 cntl_log:I_cntl_log|Mux0~86 dout_mux:I_dout_mux|Mux0~75 dout_mux:I_dout_mux|Mux0~76 dout_mux:I_dout_mux|Mux0~77 DOUT[7] } { 0.000ns 0.000ns 3.745ns 1.731ns 0.998ns 0.267ns 2.341ns } { 0.000ns 1.240ns 0.879ns 0.879ns 0.879ns 0.358ns 2.410ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}