3 freq.vhd

3倍频实用稳定算法的VHDL实现（XILINX CPLD）

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity p2s is
   PORT(
            reset    	: in std_logic;                          
            clk_in   	: in std_logic;                           
            clk_out     	: out std_logic;
            lr_shift                   : in std_logic;
            vsync                   : in std_logic;
            hsync                   : in std_logic;         
            vsync_out           : out std_logic;
            hsync_out           : out std_logic;                    
            R_in                       : in std_logic_vector(5 downto 0);
            G_in                       : in std_logic_vector(5 downto 0);
            B_in                       : in std_logic_vector(5 downto 0);
            data_out              : out std_logic_vector(5 downto 0)
                 );
end p2s;


architecture arch of p2s is

   signal  R_reg, G_reg, B_reg, data_out1  : std_logic_vector(5 downto 0);
   signal  pll_clk, pll_clk1, pll_clk2, pll_clk3 : std_logic;           
   signal clk1, clk2, clk3, clk4, clk5, clk6, clk7, clk8, clk9,clk10, clk11, clk12, clk13, clk14, clk15, clk16, clk17, clk18, clk19, clk20 : std_logic;
   signal pll_d, pll_d1, pll_d2 , pll_xor1, pll_xor2, pll_xor3, pll_xor1_1, pll_xor2_1, pll_xor3_1:  std_logic;
   signal  pll_sel:  std_logic_vector(1 downto 0);
   signal hsync_d1  ,hsync_d2  ,hsync_d3  ,hsync_d4  ,hsync_d5  ,hsync_d6, hsync_d7   :  std_logic;
   signal hsync_d8  ,hsync_d9  ,hsync_d10  ,hsync_d11  ,hsync_d12  ,hsync_d13, hsync_d14   :  std_logic;  
   signal vsync_d1  ,vsync_d2  ,vsync_d3  ,vsync_d4, vsync_d5 , vsync_d6, hsync_lr     :  std_logic;
   signal vsync_d7  ,vsync_d8  ,vsync_d9  ,vsync_d10, vsync_d11 , vsync_d12                 :  std_logic;
   signal vsync_d13  ,vsync_d14  ,vsync_d15  ,vsync_d16, vsync_d17 , vsync_d18          :  std_logic;

 begin
 
--******************** clk delay *********************
 process(reset, clk_in)
 begin
   if reset='1' then      
       pll_d2<= not clk_in;
       clk1 <= clk_in;
       clk2 <= clk1;
       clk3 <= clk2;
       clk4 <= clk3;
       clk5 <= clk4;
       clk6 <= clk5;
       clk7 <= clk6;
       clk8 <= clk7;
       clk9 <= clk8;        
       clk10<= clk9;
       clk11<= clk10;
       clk12<= clk11;
       clk13<= clk12;
       clk14<= clk13;
       clk15<= clk14;
       clk16<= clk15;
                           
  else
       clk1 <= clk1;
       clk2 <= clk2;
       clk3 <= clk3;
       clk4 <= clk4;
       clk5 <= clk5;
       clk6 <= clk6;
       clk7 <= clk7;
       clk8 <= clk8;
       clk9 <= clk9;   
       clk10<= clk10;
       clk11<= clk11;
       clk12<= clk12;
       clk13<= clk13;
       clk14<= clk14;
       clk15<= clk15;
       clk16<= clk16;

  end if;
 end process;
  
   pll_d<=clk8;   
   pll_d1<=clk16;        
   pll_xor1<=pll_d xor clk_in;
   pll_xor2<=pll_d xor pll_d1;
   pll_xor3<=pll_d1 xor pll_d2;
   pll_xor1_1<=    pll_xor1 and (not pll_d1);     
   pll_xor2_1<=    pll_xor2 and pll_d1;
   pll_xor3_1<=    pll_xor3 and pll_d;    

   pll_clk1<=pll_xor1_1;
   pll_clk3<=pll_xor2_1;
   pll_clk2<=pll_xor3_1;
 
   pll_clk <= pll_xor1_1 or  pll_xor2_1 or  pll_xor3_1;


--********************* Parallel to Series ************************** 
 process( clk_in)
 begin
      if clk_in'event and clk_in='1' then
      R_reg<=R_in;
      G_reg<=G_in;
      B_reg<=B_in;                       
  end if;
 end process;


--********************  Synchronous with hsync *****************
process(hsync, pll_clk)
begin
if hsync='0' then
    pll_sel<="11";
elsif pll_clk'event and pll_clk='0' then
      if pll_sel="10" then
         pll_sel<="00";
      else 
         pll_sel<=pll_sel +'1';
      end if;
end if;
end process;      



--*************** Data out with pll_clk ********************8
 process(pll_sel, lr_shift )
 begin       
 if lr_shift='0' then
       case  pll_sel is  
         when "00" => -- up to down BGR
         	data_out1 <=  B_reg; 
         when "01" => 
         	data_out1 <=  G_reg; 
         when "10" => 
         	data_out1 <=  R_reg;  
         when others =>
         	data_out1 <= "000000"; 
         end case;
  else 
         case  pll_sel is  
         when "00" =>  -- up to down RGB
         	data_out1 <=  R_reg; 
         when "01" => 
         	data_out1 <=  G_reg; 
         when "10" => 
         	data_out1 <=  B_reg; 
         when others =>
         	data_out1 <= "000000"; 
         end case;
    end if;         
end process;
 
-- *********** Vsync Delay ********************** 
 process(hsync, vsync)
 begin       
 if hsync'event and hsync='0' then
   vsync_d1    <=vsync;            
   vsync_d2    <=vsync_d1;     
   vsync_d3    <=vsync_d2;     
   vsync_d4    <=vsync_d3;      
   vsync_d5    <=vsync_d4;     
   vsync_d6    <=vsync_d5;         
   vsync_d7    <=vsync_d6;     
   vsync_d8    <=vsync_d7;     
   vsync_d9    <=vsync_d8;      
   vsync_d10  <=vsync_d9;     
   vsync_d11  <=vsync_d10;    
   vsync_d12  <=vsync_d11;    
   vsync_d13    <=vsync_d12;         
   vsync_d14    <=vsync_d13;     
   vsync_d15    <=vsync_d14;     
   vsync_d16    <=vsync_d15;      
   vsync_d17  <=vsync_d16;     
   vsync_d18  <=vsync_d17;    
   end if;
   end process;
       
 -- *************** Hsync Delay *********************
 process(clk_in, hsync)
 begin       
 if clk_in'event and clk_in='1' then
   hsync_d1    <=hsync;            
   hsync_d2    <=hsync_d1;     
   hsync_d3    <=hsync_d2;     
   hsync_d4    <=hsync_d3;          
   hsync_d5    <=hsync_d4;     
   hsync_d6    <=hsync_d5;    
   hsync_d7    <=hsync_d6;  
   end if;
   end process;
   
 
 -- ****************** Output *******************
 process(clk_in, hsync)
 begin
 if reset='1' 
   then    -- Normal Output 
   vsync_out    <= vsync_d2; 
   hsync_out    <=hsync_d6;            
   data_out       <=data_out1;
   clk_out          <=pll_clk ;
   else   -- Disable Output; 
   vsync_out    <= '0'; 
   hsync_out    <='0';            
   data_out       <="ZZZZZZ";
   clk_out          <='0';
   end if;
 end process;


end arch;

-- Type STD_LOGIC is below:
-- 'X' : Forcing Unknow;
-- '0' : Forcing 0 (Low level);
-- '1' : Forcing 1 (High Level);
-- 'Z' : High Impedance;
-- 'L' : Weak 0;
-- 'H' : Weak 1;
-- '-' : Don't care;
-- Note: The signal of clk_out don't set to high impedance.
-- Sometimes clk_out will be output.