📄 mt46v16m16.vhd
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IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. BL/2 cycles after command
IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Read_precharge(0) := '0';
END IF;
END IF;
IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Read_precharge(1) := '0';
END IF;
END IF;
IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Read_precharge(2) := '0';
END IF;
END IF;
IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Read_precharge(3) := '0';
END IF;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. Two clock after last burst
-- Since tWR is time base, the model will compensate tRP
IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW - ((2 * tCK) - tWR);
Write_precharge(0) := '0';
END IF;
END IF;
IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW - ((2 * tCK) - tWR);
Write_precharge(1) := '0';
END IF;
END IF;
IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW - ((2 * tCK) - tWR);
Write_precharge(2) := '0';
END IF;
END IF;
IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW - ((2 * tCK) - tWR);
Write_precharge(3) := '0';
END IF;
END IF;
END IF;
--
-- DLL Counter
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
IF (DLL_Reset = '1' AND DLL_done = '0') THEN
DLL_count := DLL_count + 1;
IF (DLL_count >= 200) THEN
DLL_done := '1';
END IF;
END IF;
END IF;
--
-- Control Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
-- Record current tRFC time
RFC_chk := NOW;
END IF;
-- Extended Load Mode Register
IF Ext_mode_enable = '1' THEN
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
IF (Addr (0) = '0') THEN
DLL_enable := '1';
ELSE
DLL_enable := '0';
END IF;
END IF;
-- Precharge to EMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Extended Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Extended Load Register"
SEVERITY WARNING;
-- LMR/EMR to EMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Extended Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
-- Register mode
Mode_reg <= Addr;
-- DLL Reset
IF (DLL_enable = '1' AND Addr (8) = '1') THEN
DLL_reset := '1';
DLL_done := '0';
DLL_count := 0;
ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
ASSERT (FALSE)
REPORT "DLL is ENABLE: DLL RESET is require"
SEVERITY WARNING;
ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
ASSERT (FALSE)
REPORT "DLL is DISABLE: DLL RESET will be ignored"
SEVERITY WARNING;
END IF;
-- Precharge to LMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Load Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Load Mode Register"
SEVERITY WARNING;
-- LMR/ELMR to LMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid Burst Length
ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
(Addr (2 DOWNTO 0) = "010") OR -- BL = 4
(Addr (2 DOWNTO 0) = "011")) -- BL = 8
REPORT "Invalid Burst Length during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid CAS Latency
ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
(Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
REPORT "Invalid CAS Latency during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
-- Activate an OPEN bank can corrupt data
ASSERT ((Ba = "00" AND Act_b0 = '0') OR
(Ba = "01" AND Act_b1 = '0') OR
(Ba = "10" AND Act_b2 = '0') OR
(Ba = "11" AND Act_b3 = '0'))
REPORT "Bank is already activated - data can be corrupted"
SEVERITY WARNING;
-- Activate Bank 0
IF Ba = "00" AND Pc_b0 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk0 >= tRC)
REPORT "tRC violation during Activate Bank 0"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := Addr;
RC_chk0 := NOW;
RCD_chk0 := NOW;
RAS_chk0 := NOW;
RAP_chk0 := NOW;
END IF;
-- Activate Bank 1
IF Ba = "01" AND Pc_b1 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk1 >= tRC)
REPORT "tRC violation during Activate Bank 1"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := Addr;
RC_chk1 := NOW;
RCD_chk1 := NOW;
RAS_chk1 := NOW;
RAP_chk1 := NOW;
END IF;
-- Activate Bank 2
IF Ba = "10" AND Pc_b2 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk2 >= tRC)
REPORT "tRC violation during Activate Bank 2"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := Addr;
RC_chk2 := NOW;
RCD_chk2 := NOW;
RAS_chk2 := NOW;
RAP_chk2 := NOW;
END IF;
-- Activate Bank 3
IF Ba = "11" AND Pc_b3 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk3 >= tRC)
REPORT "tRC violation during Activate Bank 3"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := Addr;
RC_chk3 := NOW;
RCD_chk3 := NOW;
RAS_chk3 := NOW;
RAP_chk3 := NOW;
END IF;
-- Activate Bank A to Activate Bank B
IF (Prev_bank /= Ba) THEN
ASSERT (NOW - RRD_chk >= tRRD)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- AutoRefresh to Activate
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Activate"
SEVERITY WARNING;
-- Record Variables for Checking Violation
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